Motorola MC68HC908AB32 User Manual

Serial Communications Interface Module (SCI)
I/O Registers
MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA Serial Communications Interface Module (SCI) 269
15.9.4 SCI Status Register 1
SCI status register 1 (SCS1) contains flags to signal these conditions:
• Transfer of SCDR data to transmit shift register complete
• Transmission complete
• Transfer of receive shift register data to SCDR complete
• Receiver input idle
• Receiver overrun
• Noisy data
• Framing error
• Parity error
SCTE — SCI Transmitter Empty Bit
This clearable, read-only bit is set when the SCDR transfers a
character to the transmit shift register. SCTE can generate an SCI
transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,
SCTE generates an SCI transmitter CPU interrupt request. In normal
operation, clear the SCTE bit by reading SCS1 with SCTE set and
then writing to SCDR. Reset sets the SCTE bit.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
Address: $0016
Bit 7 654321Bit 0
Read: SCTE TC SCRF IDLE OR NF FE PE
Write:
Reset: 11000000
= Unimplemented
Figure 15-12. SCI Status Register 1 (SCS1)

Motorola MC68HC908AB32 Specifications

General

Brand	Motorola
Model	MC68HC908AB32
Category	Controller
Language	English