Motorola MC68HC908AB32 User Manual

Central Processor Unit (CPU)
CPU During Break Interrupts
MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA Central Processor Unit (CPU) 97
7.6.2 Stop Mode
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
7.7 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break
interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD or with
$FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
7.8 Instruction Set Summary
7.9 Opcode Map
See Table 7-2.

Motorola MC68HC908AB32 Specifications

General

Brand	Motorola
Model	MC68HC908AB32
Category	Controller
Language	English