Motorola MC68HC908AB32 User Manual

Low-Voltage Inhibit (LVI)
Functional Description
MC68HC908AB32
—
Rev. 1.0 Technical Data
MOTOROLA Low-Voltage Inhibit (LVI)
361
21.4.1 Polled LVI Operation
In applications that can operate at V
DD
levels below the LVI
TRIPF
level,
software can monitor V
DD
by polling the LVIOUT bit. In configuration
register 1, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
21.4.2 Forced Reset Operation
In applications that require V
DD
to remain above the LVI
TRIPF
level,
enabling LVI resets allows the LVI module to reset the MCU when V
DD
falls below the LVI
TRIPF
level and remains at or below that level for 9 or
more consecutive CPU cycles. In configuration register 1, the LVIPWRD
and LVIRSTD bits must be at logic 0 to enable the LVI module and to
enable LVI resets.
21.4.3 False Reset Protection
The V
DD
pin level is digitally filtered to reduce false resets due to power
supply noise. In order for the LVI module to reset the MCU, V
DD
must
remain at or below the LVI
TRIPF
level for 9 or more consecutive CPU
cycles. V
DD
must be above LVI
TRIPR
for only one CPU cycle to bring the
MCU out of reset.
Address: $FE0F
Bit 7 654321Bit 0
Read: LVIOUT 0000000
Write:
Reset: 00000000
= Unimplemented
Figure 21-2. LVI I/O Register Summary

Motorola MC68HC908AB32 Specifications

General

Brand	Motorola
Model	MC68HC908AB32
Category	Controller
Language	English