Clock Generator Module (CGM)
Technical Data MC68HC908AB32 — Rev. 1.0
138 Clock Generator Module (CGM) MOTOROLA
and require fast start-up. The following conditions apply when in manual
mode:
• ACQ is a writable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ
bit must be
clear.
• Before entering tracking mode (ACQ
= 1), software must wait a
given time, t
ACQ
(see 9.10 Acquisition/Lock Time
Specifications), after turning on the PLL by setting PLLON in the
PLL control register (PCTL).
• Software must wait a given time, t
AL
, after entering tracking mode
before selecting the PLL as the clock source to CGMOUT
(BCS = 1).
• The LOCK bit is disabled.
• CPU interrupts from the CGM are disabled.
9.4.2.4 Programming the PLL
The following procedure shows how to program the PLL.
NOTE:
The round function in the following equations means that the real
number should be rounded to the nearest integer number.
1. Choose the desired bus frequency, f
BUSDES
.
2. Calculate the desired VCO frequency (four times the desired bus
frequency).
3. Choose a practical PLL reference frequency, f
RCLK
.
4. Select a VCO frequency multiplier, N.
f
VCLKDES
4f
BUSDES
×=
N round
f
VCLKDES
f
RCLK
----------------------
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