Motorola MC68HC908AB32 - LVI Interrupts; LVI Status Register (LVISR)

Low-Voltage Inhibit (LVI)
Technical Data MC68HC908AB32
—
Rev. 1.0
362
Low-Voltage Inhibit (LVI) MOTOROLA
21.5 LVI Status Register (LVISR)
The LVI status register flags V
DD
voltages below the LVI
TRIPF
level
.
LVIOUT — LVI Output Bit
This read-only flag becomes set when V
DD
falls below the LVI
TRIPF
voltage for 32 to 40 CGMXCLK cycles. (See Table 21-1 .) Reset
clears the LVIOUT bit.
21.6 LVI Interrupts
The LVI module does not generate interrupt requests.
Address: $FE0F
Bit 7 654321Bit 0
Read: LVIOUT 0000000
Write:
Reset: 00000000
= Unimplemented
Figure 21-3. LVI Status Register (LVISR)
Table 21-1. LVIOUT Bit Indication
V
DD
LVIOUT
At level:
For number of CGMXCLK
cycles:
V
DD
> LVI
TRIPR
Any 0
V
DD
< LVI
TRIPF
< 32 CGMXCLK cycles 0
V
DD
< LVI
TRIPF
32 to 40 CGMXCLK cycles 0 or 1
V
DD
< LVI
TRIPF
> 40 CGMXCLK cycles 1
LVI
TRIPF
< V
DD
< LVI
TRIPR
Any Previous value