Motorola MC68HC908AB32 User Manual

Timer Interface Module B (TIMB)
I/O Registers
MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA Timer Interface Module B (TIMB) 215
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIMB
counter registers matches the value in the TIMB channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE = 1), clear
CHxF by reading TIMB channel x status and control register with
CHxF set and then writing a logic zero to CHxF. If another interrupt
request occurs before the clearing sequence is complete, then writing
logic zero to CHxF has no effect. Therefore, an interrupt request
cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic one to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIMB CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
Address: $0032
Bit 7 654321Bit 0
Read: CH2F
CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX
Write: 0
Reset: 00000000
Figure 12-11. TIMB Channel 2 Status and Control Register (TBSC2)
Address: $0035
Bit 7 654321Bit 0
Read: CH3F
CH3IE
0
MS3A ELS3B ELS3A TOV3 CH3MAX
Write: 0
Reset: 00000000
Figure 12-12. TIMB Channel 3 Status and Control Register (TBSC3)

Motorola MC68HC908AB32 Specifications

General

Brand	Motorola
Model	MC68HC908AB32
Category	Controller
Language	English