Clock Generator Module (CGM)
Technical Data MC68HC908AB32 — Rev. 1.0
156 Clock Generator Module (CGM) MOTOROLA
whether the PLL is within the lock mode entry tolerance ∆
LOCK
.
Therefore, the acquisition time t
ACQ
, is an integer multiple of n
ACQ
/f
RDV
,
and the acquisition to lock time t
AL
, is an integer multiple of n
TRK
/f
RDV
.
Also, since the average frequency over the entire measurement period
must be within the specified tolerance, the total time usually is longer
than t
LOCK
as calculated above.
In manual mode, it is usually necessary to wait considerably longer than
t
LOCK
before selecting the PLL clock (see 9.4.3 Base Clock Selector
Circuit), because the factors described in 9.10.2 Parametric
Influences On Reaction Time may slow the lock time considerably.
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