Motorola MC68HC908AB32

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Input/Output (I/O) Ports

Technical Data MC68HC908AB32 — Rev. 1.0

338 Input/Output (I/O) Ports MOTOROLA

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Default Chapter3
- Table of Contents3
- Contents29
Section 1. General Description30
- Introduction30
- Features30
- MCU Block Diagram31
- MC68HC908AB32 Block Diagram32
- Pin Assignments33
- 64-Pin QFP Pin Assignment33
- Pin Functions34
- Power Supply Pins (VDD and VSS )34
- Power Supply Bypassing34
- Oscillator Pins (OSC1 and OSC2)35
- External Reset Pin (RST)35
- External Interrupt Pin (IRQ)35
- Analog Power Supply Pin (VDDA )35
- Analog Ground Pin (VSSA )35
- Analog Ground Pin (AVSS /VREFL )35
- ADC Voltage Reference Pin (VREFH)36
- Analog Supply Pin (VDDAREF )36
- External Filter Capacitor Pin (CGMXFC)36
- Port a Input/Output (I/O) Pins (PTA7-PTA0)36
- Port B I/O Pins (PTB7/ATD7-PTB0/ATD0)36
- Port C I/O Pins (PTC5-PTC0)36
- Port D I/O Pins (PTD7-PTD0)37
- Port E I/O Pins (PTE7/SPSCK-Pte0/Txd)37
- Port F I/O Pins (PTF7-PTF0/TACH2)37
- Port G I/O Pins (PTG2/KBD2-PTG0/KBD0)37
- Port H I/O Pins (PTH1/KBD4-PTH0/KBD3)37
- I/O Pin Summary38
- I/O Pins Summary38
- Signal Name Conventions40
- Clock Source Summary40
- MC68HC908AB32 Rev40
Section 2. Memory Map41
- Contents41
- Introduction41
- Unimplemented Memory Locations41
- Reserved Memory Locations42
- Input/Output (I/O) Section42
- Section 4. FLASH Memory43
- Memory Map43
- Control, Status, and Data Registers45
- Vector Addresses56
Section 2. Memory Map57
- Contents57
- Introduction57
- Functional Description57
Section 3. Random-Access Memory (RAM)57
- Contents59
- Introduction59
- Functional Description59
Section 4. FLASH Memory59
- FLASH Control Register60
- FLASH Control Register (FLCR)60
- FLASH Page Erase Operation61
- FLASH Mass Erase Operation62
- FLASH Program/Read Operation63
- FLASH Block Protection64
- FLASH Programming Flowchart65
- FLASH Block Protect Register66
- FLASH Block Protect Start Address66
- FLASH Block Protect Register (FLBPR)66
- Wait Mode67
- Stop Mode67
Section 4. FLASH Memory69
- Introduction69
Section 5. EEPROM69
- Features70
- EEPROM I/O Register Summary70
- Functional Description71
- EEPROM Configuration71
- EEPROM Timebase Requirements72
- EEPROM Security Options72
- EEPROM Block Protection72
- EEPROM Programming and Erasing73
- EEPROM Array Address Blocks73
- EEPROM Programming74
- EEPROM Erasing75
- Low Power Modes76
- Wait Mode76
- Stop Mode77
- EEPROM Registers77
- EEPROM Control Register77
- EEPROM Control Register (EECR)77
- EEPROM Program/Erase Mode Select78
- EEPROM Array Configuration Register79
- EEPROM Array Configuration Register (EEACR)79
- EEPROM Non-Volatile Register80
- EEPROM Timebase Divider Register80
- EEPROM Non-Volatile Register (EENVR)80
- EEPROM Divider Register High (EEDIVH)81
- EEPROM Divider Register Low (EEDIVL)81
- EEPROM Timebase Divider Non-Volatile Register82
- EEPROM Divider Non-Volatile Register High(EEDIVHNVR)82
- EEPROM Divider Non-Volatile Register Low (EEDIVLNVR)82
Section 6. Configuration Register (CONFIG)85
- Configuration Register 1 (CONFIG1)86
- Functional Description86
- Configuration Register 2 (CONFIG2)88
  - Introduction89
Section 7. Central Processor Unit (CPU)89
- CPU Registers90
  - Features90
- Accumulator91
- CPU Registers91
- Accumulator (A)91
- Index Register92
- Stack Pointer92
- Index Register (H:X)92
- Program Counter93
- Condition Code Register93
- Stack Pointer (SP)93
- Program Counter (PC)93
- Condition Code Register (CCR)94
- Arithmetic/Logic Unit (ALU)96
- Low-Power Modes96
- Wait Mode96
- Stop Mode97
- CPU During Break Interrupts97
- Instruction Set Summary97
- Opcode Map97
- Instruction Set Summary98
- Opcode Map107
Section 8. System Integration Module (SIM)109
- Contents109
- Introduction110
- Signal Naming Conventions111
- SIM Block Diagram111
- SIM Bus Clock Control and Generation112
- Bus Timing113
- Clock Start-Up from por or LVI Reset113
- Clocks in Stop and Wait Modes113
- Reset and System Initialization113
- External Pin Reset114
- Active Resets from Internal Sources114
- PIN Bit Set Timing114
- Power-On Reset115
- Computer Operating Properly (COP) Reset116
- Illegal Opcode Reset117
- Illegal Address Reset117
- Low-Voltage Inhibit (LVI) Reset117
- SIM Counter117
- SIM Counter During Power-On Reset118
- SIM Counter During Stop Mode Recovery118
- SIM Counter and Reset States118
- Exception Control118
- Interrupts119
- Hardware Interrupts120
- SWI Instruction121
- Vector Addresses122
- Reset123
- Break Interrupts123
- Status Flag Protection in Break Mode123
- Low-Power Modes124
- Wait Mode124
- Stop Mode125
- Stop Mode Entry Timing126
- SIM Registers127
- SIM Break Status Register127
- SIM Reset Status Register128
- SIM Break Flag Control Register129
Section 9. Clock Generator Module (CGM)131
- Contents131
- Introduction132
- Features132
- Functional Description133
- Crystal Oscillator Circuit134
- Phase-Locked Loop (PLL) Circuit135
- PLL Circuits135
- Acquisition and Tracking Modes136
- Manual and Automatic PLL Bandwidth Modes136
- Programming the PLL138
- Special Programming Exceptions139
- Base Clock Selector Circuit140
  - CGM External Connections140
- CGM External Connections141
- I/O Signals142
- Crystal Amplifier Input Pin (OSC1)142
- Crystal Amplifier Output Pin (OSC2)142
- External Filter Capacitor Pin (CGMXFC)142
- PLL Analog Power Pin (VDDA )142
- MC68HC908AB32 - Rev142
- Oscillator Enable Signal (SIMOSCEN)142
  - PLL Analog Power Pin142
  - Dda142
- Crystal Output Frequency Signal (CGMXCLK)143
- CGM Base Clock Output (CGMOUT)143
- CGM CPU Interrupt (CGMINT)143
- CGM Registers143
- PLL Control Register (PCTL)144
- PLL Bandwidth Control Register (PBWC)146
- PLL Programming Register (PPG)148
- VCO Frequency Multiplier (N) Selection149
- Interrupts150
- Low-Power Modes150
- Wait Mode150
- Stop Mode151
- CGM During Break Interrupts151
- Acquisition/Lock Time Specifications151
- Acquisition/Lock Time Definitions152
- Parametric Influences on Reaction Time153
- Choosing a Filter Capacitor154
- Reaction Time Calculation155
- Contents157
- Introduction157
- Section 10. Monitor ROM (MON)157
Section 10. Monitor ROM (MON)158
- Features158
- Functional Description158
- Monitor Mode Circuit159
- Entering Monitor Mode160
- Monitor Mode Entry Conditions160
- Data Format161
- Mode Differences161
- Echoing162
- Break Signal162
- Commands163
- READ (Read Memory) Command163
- WRITE (Write Memory) Command164
- IREAD (Indexed Read) Command164
- IWRITE (Indexed Write) Command165
- READSP (Read Stack Pointer) Command165
- Baud Rate166
- RUN (Run User Program) Command166
- Monitor Baud Rate Selection166
- Security167
- Extended Security168
- Contents169
- Section 11. Timer Interface Module a (TIMA)169
- Section 11. Timer Interface Module a (TIMA)170
  - Features170
  - Introduction170
  - Functional Description171
  - Pin Name Conventions171
  - TIMA Counter Prescaler171
  - TIMA Block Diagram172
  - TIMA I/O Register Summary173
  - Input Capture174
  - Output Compare175
  - Unbuffered Output Compare175
  - Buffered Output Compare176
  - Pulse Width Modulation (PWM)177
  - Unbuffered PWM Signal Generation178
  - Buffered PWM Signal Generation179
  - PWM Initialization180
  - Interrupts181
  - Low-Power Modes181
  - Stop Mode182
  - TIMA During Break Interrupts182
  - Wait Mode182
  - I/O Signals183
  - TIMA Channel I/O Pins183
  - TIMA Clock Pin183
  - I/O Registers184
  - TIMA Status and Control Register184
  - Prescaler Selection186
  - TIMA Counter Registers186
  - TIMA Counter Modulo Registers187
  - TIMA Channel Status and Control Registers188
  - TIMA Channel 2 Status and Control Register (TASC2)189
  - Mode, Edge, and Level Selection191
  - TIMA Channel Registers192
  - TIMA Channel 1 Register High (TACH1H)193
  - TIMA Channel 3 Register High (TACH3H)194
- Section 12. Timer Interface Module B (TIMB)195
  - Contents195
  - Features196
  - Introduction196
  - Functional Description197
  - Pin Name Conventions197
  - TIMB Counter Prescaler197
  - TIMB Block Diagram198
  - TIMB I/O Register Summary199
  - Input Capture200
  - Output Compare201
  - Unbuffered Output Compare201
  - Buffered Output Compare202
  - Pulse Width Modulation (PWM)203
  - Unbuffered PWM Signal Generation204
  - Buffered PWM Signal Generation205
  - PWM Initialization206
  - Interrupts207
  - Low-Power Modes207
  - Stop Mode208
  - TIMB During Break Interrupts208
  - Wait Mode208
  - I/O Signals209
  - TIMB Channel I/O Pins209
  - TIMB Clock Pin209
  - I/O Registers210
  - TIMB Status and Control Register210
  - TIMB Counter Registers212
  - TIMB Counter Modulo Registers213
  - TIMB Channel Status and Control Registers214
  - TIMB Channel 2 Status and Control Register (TBSC2)215
  - Mode, Edge, and Level Selection217
  - TIMB Channel Registers218
  - TIMB Channel 1 Register High (TBCH1H)219
  - TIMB Channel 3 Register High (TBCH3H)220
  - Contents221
  - Introduction221
Section 13. Programmable Interrupt Timer (PIT)221
- Features222
- Functional Description222
- PIT Counter Prescaler223
- Low-Power Modes224
- PIT During Break Interrupts224
- Stop Mode224
- Wait Mode224
- I/O Registers225
- PIT Status and Control Register225
- PIT Counter Registers227
- PIT Counter Modulo Registers228
- Contents229
Section 14. Analog-To-Digital Converter (ADC)229
- Features230
- Introduction230
- Functional Description231
- ADC Port I/O Pins232
- Conversion232
- Conversion Time232
- Voltage Conversion232
- Accuracy and Precision233
- I/O Signals233
- Interrupts233
- Low-Power Modes233
- Stop Mode233
- Wait Mode233
- ADC Analog Ground Pin (AVSS /V REFL )234
- ADC Analog Power Pin234
- ADC Voltage in234
- ADC Voltage Reference High Pin234
- Adin )234
- Ddaref234
- I/O Registers234
- Refh )234
- ADC Status and Control Register (ADSCR)235
- Mux Channel Select236
- ADC Clock Register (ADCLK)237
- ADC Data Register (ADR)237
- ADC Clock Divide Ratio238
Section 15. Serial Communications Interface239
Section 14. Analog-To-Digital Converter (ADC)239
- Contents239
Module (SCI)239
- Features240
- Introduction240
- Functional Description242
- Pin Name Conventions242
- SCI Module Block Diagram243
- SCI I/O Register Summary244
- Data Format245
- Transmitter245
- SCI Transmitter246
- Character Length247
- Character Transmission247
- Break Characters248
- Idle Characters248
- Inversion of Transmitted Output249
- Transmitter Interrupts249
- Character Length250
- Character Reception250
- Receiver250
- SCI Receiver Block Diagram251
- Data Sampling252
- Start Bit Verification253
- Baud Rate Tolerance254
- Framing Errors254
- Slow Data255
- Fast Data256
- Receiver Wakeup257
- Error Interrupts258
- Receiver Interrupts258
- Low-Power Modes259
- MC68HC908AB32 - Rev259
- Stop Mode259
- Wait Mode259
- I/O Signals260
- Pte0/Txd (Transmit Data)260
- Pte1/Rxd (Receive Data)260
- SCI During Break Module Interrupts260
- I/O Registers261
- SCI Control Register 1261
- SCI Control Register 1 (SCC1)262
- SCI Control Register 2264
- SCI Control Register 2 (SCC2)265
- SCI Control Register 3267
- SCI Status Register 1269
- Flag Clearing Sequence272
- SCI Status Register 2273
- SCI Data Register274
- SCI Baud Rate Register275
- SCI Baud Rate Selection276
- SCI Baud Rate Selection Examples277
- Contents279
Section 16. Serial Peripheral Interface Module (SPI)279
- Features280
- Introduction280
- Functional Description281
- Pin Name Conventions and I/O Register Addresses281
- SPI Module Block Diagram282
- Master Mode283
- Slave Mode284
- Clock Phase and Polarity Controls285
- Transmission Formats285
- Transmission Format When CPHA = 0286
- Transmission Format (CPHA = 0)287
- Transmission Format When CPHA = 1288
- Transmission Initiation Latency289
- Transmission Start Delay (Master)290
- Queuing Transmission Data291
- Error Conditions292
- Overflow Error292
- Missed Read of Overflow Condition293
- Mode Fault Error294
- Interrupts296
- SPI Interrupt Request Generation297
- Resetting the SPI298
- Low-Power Modes299
- Stop Mode299
- Wait Mode299
- I/O Signals300
- SPI During Break Interrupts300
- MISO (Master In/Slave Out)301
- MOSI (Master Out/Slave In)301
- SPSCK (Serial Clock)302
- SS (Slave Select)302
- CGND (Clock Ground)303
- I/O Registers304
- SPI Control Register304
- SPI Status and Control Register306
- SPI Master Baud Rate Selection308
- SPI Data Register309
- Contents311
Section 17. Input/Output (I/O) Ports311
- Introduction312
- Port Control Register Bits Summary314
- Data Direction Register a (DDRA)316
- Port a316
- Port a Data Register (PTA)316
- Port a I/O Circuit317
- Port B318
- Port B Data Register (PTB)318
- Data Direction Register B (DDRB)319
- Port C320
- Port C Data Register (PTC)320
- Data Direction Register C (DDRC)321
- Port C I/O Circuit322
- Port D323
- Port D Data Register (PTD)323
- Data Direction Register D (DDRD)324
- Port D Input Pullup Enable Register (PTDPUE)325
- Port E326
- Port E Data Register (PTE)326
- Data Direction Register E (DDRE)328
- Port F329
- Port F Data Register (PTF)329
- Data Direction Register F (DDRF)330
- Port F I/O Circuit331
- Port F Input Pullup Enable Register (PTFPUE)332
- Port G332
- Port G Data Register (PTG)332
- Data Direction Register G (DDRG)333
- Port G I/O Circuit334
- Data Direction Register H (DDRH)335
- Port H335
- Port H Data Register (PTH)335
- Data Direction Register H (DDRH)336
- Port H Pin Functions337
- Contents339
- Features339
- Introduction339
Section 18. External Interrupt (IRQ)339
- Functional Description340
- IRQ Module Block Diagram341
- IRQ Pin342
- IRQ Status and Control Register (ISCR)343
- IRQ Module During Break Interrupts344
- Contents345
- Introduction345
Section 19. Keyboard Interrupt Module (KBI)345
- Features346
- I/O Pins346
- Functional Description347
- Keyboard Initialization349
- Keyboard Status and Control Register349
- Keyboard Status and Control Register (KBSCR)350
- Keyboard Interrupt Enable Register351
- Stop Mode351
- Wait Mode351
- Keyboard Module During Break Interrupts352
- Introduction353
Section 20. Computer Operating Properly (COP)353
- Functional Description354
- Cgmxclk355
- COPCTL Write355
- I/O Signals355
- Power-On Reset355
- STOP Instruction355
- COPD (COP Disable)356
- COPRS (COP Rate Select)356
- Internal Reset356
- Reset Vector Fetch356
- COP Control Register357
- Interrupts357
- Low-Power Modes357
- Monitor Mode357
- COP Module During Break Mode358
- Stop Mode358
- Wait Mode358
Section 20. Computer Operating Properly (COP)359
- Contents359
- Features359
- Introduction359
- MC68HC908AB32 - Rev359
Section 21. Low-Voltage Inhibit (LVI)359
- Functional Description360
- False Reset Protection361
- Forced Reset Operation361
- Polled LVI Operation361
- LVI Interrupts362
- LVI Status Register (LVISR)362
- Low-Power Modes363
- Stop Mode363
- Wait Mode363
- Contents365
- Introduction365
Section 22. Break Module (BRK)365
- Features366
- Functional Description366
- Break Module Block Diagram367
- COP During Break Interrupts368
- CPU During Break Interrupts368
- Flag Protection During Break Interrupts368
- Low-Power Modes368
- PIT, TIMA, and TIMB During Break Interrupts368
- Wait Mode368
- Break Module Registers369
- Break Status and Control Register369
- Stop Mode369
- Break Address Registers370
- SIM Break Status Register370
- SIM Break Status Register (SBSR)371
- SIM Break Flag Control Register372
  - Introduction373
Section 23. Electrical Specifications373
- Absolute Maximum Ratings374
- Functional Operating Range375
- Thermal Characteristics375
- V DC Electrical Characteristics376
- EEPROM and Memory Characteristics377
- Timer Interface Module Characteristics378
- V Control Timing378
- ADC Characteristics379
- SPI Characteristics380
- SPI Master Timing381
- SPI Slave Timing382
- CGM Component Information383
- CGM Operating Conditions383
- Clock Generation Module Characteristics383
- CGM Acquisition/Lock Time Information384
- FLASH Memory Characteristics385
- Contents387
- Introduction387
Section 24. Mechanical Specifications387
- 64-Pin Plastic Quad Flat Pack (QFP)388
Section 25. Ordering Information389

Motorola MC68HC908AB32 - Page 338

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