Central Processor Unit (CPU)
Opcode Map
MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA Central Processor Unit (CPU) 99
BCS
rel
Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 +
rel
? (C) = 1 ––––––REL 25 rr 3
BEQ
rel
Branch if Equal PC ← (PC) + 2 +
rel
? (Z) = 1 ––––––REL 27 rr 3
BGE
opr
Branch if Greater Than or Equal To
(Signed Operands)
PC ← (PC) + 2 +
rel
? (N ⊕ V) = 0 ––––––REL 90 rr 3
BGT
opr
Branch if Greater Than (Signed
Operands)
PC ← (PC) + 2 +
rel
? (Z) | (N ⊕ V) =
0
––––––REL 92 rr 3
BHCC
rel
Branch if Half Carry Bit Clear PC ← (PC) + 2 +
rel
? (H) = 0 ––––––REL 28 rr 3
BHCS
rel
Branch if Half Carry Bit Set PC ← (PC) + 2 +
rel
? (H) = 1 ––––––REL 29 rr 3
BHI
rel
Branch if Higher PC ← (PC) + 2 +
rel
? (C) | (Z) = 0 ––––––REL 22 rr 3
BHS
rel
Branch if Higher or Same
(Same as BCC)
PC ← (PC) + 2 +
rel
? (C) = 0 ––––––REL 24 rr 3
BIH
rel
Branch if IRQ Pin High PC ← (PC) + 2 +
rel
? IRQ = 1 ––––––REL 2F rr 3
BIL
rel
Branch if IRQ Pin Low PC ← (PC) + 2 +
rel
? IRQ = 0 ––––––REL 2E rr 3
BIT #
opr
BIT
opr
BIT
opr
BIT
opr
,X
BIT
opr
,X
BIT ,X
BIT
opr
,SP
BIT
opr
,SP
Bit Test (A) & (M) 0 – – ↕↕–
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A5
B5
C5
D5
E5
F5
9EE5
9ED5
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
BLE
opr
Branch if Less Than or Equal To
(Signed Operands)
PC ← (PC) + 2 +
rel
? (Z) | (N ⊕ V) =
1
––––––REL 93 rr 3
BLO
rel
Branch if Lower (Same as BCS) PC ← (PC) + 2 +
rel
? (C) = 1 ––––––REL 25 rr 3
BLS
rel
Branch if Lower or Same PC ← (PC) + 2 +
rel
? (C) | (Z) = 1 ––––––REL 23 rr 3
BLT
opr
Branch if Less Than (Signed Operands) PC ← (PC) + 2 +
rel
? (N ⊕ V) =1 ––––––REL 91 rr 3
BMC
rel
Branch if Interrupt Mask Clear PC ← (PC) + 2 +
rel
? (I) = 0 ––––––REL 2C rr 3
BMI
rel
Branch if Minus PC ← (PC) + 2 +
rel
? (N) = 1 ––––––REL 2B rr 3
BMS
rel
Branch if Interrupt Mask Set PC ← (PC) + 2 +
rel
? (I) = 1 ––––––REL 2D rr 3
BNE
rel
Branch if Not Equal PC ← (PC) + 2 +
rel
? (Z) = 0 ––––––REL 26 rr 3
BPL
rel
Branch if Plus PC ← (PC) + 2 +
rel
? (N) = 0 ––––––REL 2A rr 3
BRA
rel
Branch Always PC ← (PC) + 2 +
rel
––––––REL 20 rr 3
Table 7-1. Instruction Set Summary (Continued)
Source
Form
Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VHINZC