Appendix A: PS/2 Keyboard Wedge
Operational Overview
A PS/2 Keyboard Wedge functions by interposing itself on the PS/2 conforming keyboard
clock and keyboard data lines that would typically connect just the keyboard to the host
terminal. The wedge has the ability to monitor the PS/2 keyboard clock and data lines without
affecting standard operations between PS/2 keyboard and host terminal. When the wedge has
data to send to the host terminal it can put the PS/2 keyboard on hold and switch itself into the
circuit. When the wedge is in the circuit it communicates to the host terminal by sending scan
codes. When the wedge has finished sending its packet of scan codes it takes itself out of the
circuit and releases the PS/2 keyboard from hold. The PS/2 keyboard and host terminal are
then able to communicate as before.
At the hardware level the PS/2 keyboard interface consists of three open-collector lines:
KBCLK PCCLK and DATA. The PS/2 keyboard or wedge device is always responsible for
toggling the clock line to clock data in or out. The basic bit package of a transmission from
wedge (or PS/2 keyboard) to the host terminal is 1 start bit, 8 data bits, 1 parity bit, and 1 stop
bit. Transmissions from host terminal to wedge (or PS/2 keyboard) uses the same bit
packaging but with a single acknowledge bit appended by the wedge (or PS/2 keyboard) after
the stop bit.
The wedge interface is always in one of two states, Wedge-In, or Wedge-Out. These states are
described below.
Wedge-In State
When in Wedge-In state, the wedge holds the clock line to the PS/2 keyboard low to put the
keyboard on hold. At the same time the wedge interposes itself on the clock and data lines
going to the host terminal. During Wedge-In, the wedge communicates with the host terminal
by sending data, acknowledging data sent by the host terminal, and responding to host terminal
commands. Which commands the wedge responds to depends on the state of the PS/2
Keyboard Emulation programming bit (see programmables section below). PS/2 Keyboard
Emulation mode is described in detail below.
Wedge-Out State
When in Wedge-Out state, the wedge does not control either clock or data lines, however, it is
able to monitor these lines. In particular, when the scanner generates a new packet of scan
codes for transmission over the wedge interface, the wedge must wait for the PS/2 keyboard
interface to be in the idle state (idle state is defined as clock high and data high) for at least 1
millisecond before transitioning to the Wedge-In state.
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