When multiple (n) messages are added to the Tx FIFO, they are written to n consecutive
Tx Buffers starting with the Put Index. The transmissions are then requested via TXBAR.
The Put Index is then cyclically incremented by n. The number of requested Tx buffers
should not exceed the number of free Tx Buffers as indicated by the Tx FIFO Free Level.
When a transmission request for the Tx Buffer referenced by the Get Index is cancelled,
the Get Index is incremented to the next Tx Buffer with pending transmission request and
the Tx FIFO Free Level is recalculated. When transmission cancellation is applied to any
other Tx Buffer, the Get Index and the FIFO Free Level remain unchanged.
A Tx FIFO element allocates Element Size 32-bit words in the Message RAM. Therefore
the start address of the next available (free) Tx FIFO Buffer is calculated by adding Tx
FIFO/Queue Put Index TXFQS.TFQPI (0…31) x Element Size to the Tx Buffer Start
Address TXBC[TBSA].
3.5.5.4 Tx Queue
Tx Queue operation is configured by programming TXBC[TFQM] to 1. Messages stored
in the Tx Queue are transmitted starting with the message with the lowest Message ID
(highest priority). In case that multiple Queue Buffers are configured with the same
Message ID, the Queue Buffer with the lowest buffer number is transmitted first.
New messages have to be written to the Tx Buffer referenced by the Put Index
TXFQS[TFQPI]. An Add Request cyclically increments the Put Index to the next free Tx
Buffer. In case that the Tx Queue is full (TXFQS[TFQF] = 1), the Put Index is not valid
and no further message should be written to the Tx Queue until at least one of the
requested messages has been sent out or a pending transmission request has been
cancelled.
The application may use register TXBRP instead of the Put Index and may place
messages to any Tx Buffer without pending transmission request.
A Tx Queue Buffer allocates Element Size 32-bit words in the Message RAM. Therefore
the start address of the next available (free) Tx Queue Buffer is calculated by adding Tx
FIFO/Queue Put Index TXFQS[TFQPI] (0…31) x Element Size to the Tx Buffer Start
Address TXBC[TBSA].
Chapter 3 Modular CAN (M_CAN)
MPC5777C Reference Manual Addendum, Rev. 1, 12/2015
Freescale Semiconductor, Inc. 111
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