1303
CS-series Instruction Execution Times and Number of Steps Section 4-1
Note 1. When a double-length operand is used, add 1 to the value shown in the
length column in the following table.
2. Supported only by CPU Units Ver. 2.0 or later.
4-1-17 Subroutine Instructions
Note When a double-length operand is used, add 1 to the value shown in the length
column in the following table.
4-1-18 Interrupt Control Instructions
Note When a double-length operand is used, add 1 to the value shown in the length
column in the following table.
4-1-19 Step Instructions
Note When a double-length operand is used, add 1 to the value shown in the length
column in the following table.
Instruction Mnemonic Code Length
(steps)
(See note.)
ON execution time (µs) Conditions
CPU-6@HCPU-4@HCPU-6@ CPU-4@
SUBROUTINE CALL SBS 091 2 1.26 1.96 17.0 17.0 ---
SUBROUTINE
ENTRY
SBN 092 2 --- --- --- --- ---
SUBROUTINE
RETURN
RET 093 1 0.86 1.60 20.60 20.60 ---
MACRO MCRO 099 4 23.3 23.3 23.3 23.3 ---
GLOBAL SUBROU-
TINE CALL
GSBN 751 2 --- --- --- --- ---
GLOBAL SUBROU-
TINE ENTRY
GRET 752 1 1.26 1.96 --- --- ---
GLOBAL SUBROU-
TINE RETURN
GSBS 750 2 0.86 1.60 --- --- ---
Instruction Mnemonic Code Length
(steps)
(See note.)
ON execution time (µs) Conditions
CPU-6@HCPU-4@HCPU-6@ CPU-4@
SET INTERRUPT
MASK
MSKS 690 3 25.6 38.4 39.5 39.5 ---
READ INTER-
RUPT MASK
MSKR 692 3 11.9 11.9 11.9 11.9 ---
CLEAR INTER-
RUPT
CLI 691 3 27.4 41.3 41.3 41.3 ---
DISABLE INTER-
RUPTS
DI 693 1 15.0 16.8 16.8 16.8 ---
ENABLE INTER-
RUPTS
EI 694 1 19.5 21.8 21.8 21.8 ---
Instruction Mnemonic Code Length
(steps)
(See note.)
ON execution time (µs) Conditions
CPU-6@HCPU-4@HCPU-6@ CPU-4@
STEP
DEFINE
STEP 008 2 17.4 20.7 27.1 27.1 Step control bit
ON
11.8 13.7 24.4 24.4 Step control bit
OFF
STEP
START
SNXT 009 2 6.6 7.3 10.0 10.0 ---
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