Schweitzer Engineering SEL-351P - IRIG-B Time Code

10-2 Serial Port Communications and Commands Date Code 990215
SEL-351P Manual Técnico
P ORT C ONNECTOR AND C OMMUNICATIONS C ABLES
Figure SECTION 10: .1: DB-9 Connector Pinout for EIA-232 Serial Ports
IRIG-B Time Code
Table SECTION 10: .1 shows that you can input demodulated IRIG-B time synchronization
code into SEL-351P Serial Port 2 to synchronize the recloser control’s built-in clock to a
synchronized master clock. This is handled adeptly by connecting Serial Port 2 of the SEL-351P
to an SEL-2020 Communications Processor with Cable C273A (see cable diagrams that follow in
this section). The SEL-2020 distributes demodulated IRIG-B time code through all of its 16 rear
EIA-232 serial ports.
Demodulated IRIG-B time code can also be input into the Serial Port 1 compression connector.
If demodulated IRIG-B time code is input into this connector, it should not be input into Serial
Port 2 and vice versa.
Table SECTION 10: .1: Pinout Functions for EIA-232 Serial Ports 2, 3, and F
Pin Port 2 Port 3 Port F
Wake-Up
Port
1 N/C or +5 Vdc
1
N/C or +5 Vdc
1
N/C DCD
2 RXD RXD RXD RXD
3 TXD TXD TXD N/C
4 +IRIG-B N/C N/C N/C
5 GND GND GND GND
6 -IRIG-B N/C N/C DSR
7 RTS RTS RTS N/C
8 CTS CTS CTS CTS
9 GND GND GND N/C
1
See Table 2.6 in Section 2: Additional Installation Details and Figure 19 in the
SEL-351P Quick-Start Installation and User’s Guide.
(female chassis connector, as viewed from outside panel)