Appendix B BIOS POST Codes B-3
10h Auto-detect flash type to load appropriate flash R/W codes into the
run -time area in F000 for ESCD & DMI support.
11h Reserved.
12h Use walking 1’s algorithm to check out interface in CMOS circuitry.
Also, set real-time clock power status, and then check for override.
13h Reserved.
14h Program chipset default values into chipset. Chipset default values
are MODBINable by OEM customers.
15h Reserved.
16h Initial onboard clock generator if Early_Init_Onboard_Generator is
defined. See also POST 26h.
17h Reserved.
18h Detect CPU information including brand, SMI type (Cyrix or Intel),
and CPU level (586 or 686).
19h Reserved.
1Ah Reserved.
1Bh Initial interrupts vector table. If no special specified, all hardware
interrupts are directed to SPURIOUS_INT_HDLR and software
interrupts to SPURIOUS_soft_HDLR.
1Ch Reserved.
1Dh Initial EARLY_PM_INIT switch.
1Eh Reserved.
1Fh Load keyboard matrix (notebook platform).
20h Reserved.
21h HPM initialization (notebook platform).
22h Reserved.
23h 1. Check validity of RTC value. For example, a value of 5Ah is an
invalid value for RTC minute.
2. Load CMOS settings into BIOS stack. If CMOS checksum fails, use
default value instead.
24h Prepare BIOS resource map for PCI and PnP use. If ESCD is valid,
consider the ESCD’s legacy information.
TABLE B-1 BIOS Port 80 POST Codes (Continued)
Post Code Description
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