Bit 5
Processor supports DPRT-2 (dual-PRT) algorithms
Bit 6
Could not generate the requested phase sequence
Bit 7
Unused
Bits 8-11
User-defined Major Modes 1 ... 4 are supported
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
---------------------------------------------------------------
| | | | | | | | | | | | | | | | |
| Signed trigger slew in hundredths of microseconds | Output 56
|----------------------------------------------------------------|
This is the same format that is used by the SETSLEW command to set the current trigger
slew. See 8.26 Set Trigger Timing Slew (SETSLEW) (page 312).
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
---------------------------------------------------------------
| | | | | | | | | | | | | | | | |
| Polarization Algorithm Choices | Output 57
|----------------------------------------------------------------|
Bit 0
Use H transmissions for (T, Z, V, W)
Bit 1
Use V transmissions for (T, Z, V, W)
Bit 2
Use Co-Pol reception for (T, Z, V, W)
Bit 3
Use Cross-Pol reception for (T, Z, V, W)
Bit 4
Correct all polar Parameters for noise
Bit 5
Use filtered data for all polar parameters
Bit 6
Sign convention for PhiDP
Bit 7
Z and Z
dr
are corrected for attenuation using PhiDP
Chapter 8 – Host Computer Commands
287
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