UG071 (v1.12) June 2, 2017 www.xilinx.com Virtex-4 FPGA Configuration User Guide
01/19/06 1.4 Completed grammatical and style edits for clarity and compliance to Xilinx
documentation standards.
Added preface, not included in previous versions. Corrected Table 1-1, page 13 (Note 2.).
Added “HSWPEN has a weak pull-up prior to and during configuration” to Table 1-2,
page 14. Clarified first paragraph of “Clear Configuration Memory (Step 2,
Initialization),” page 16. Clarified title of Table 1-10, page 22 (status register), to
differentiate from Figure 1-10 (signal sequencing). Added descriptions for GWE, GTS,
EOS, DCI_MATCH, and DCM_LOCK to Table 1-10, page 22. Added “ICAP is not
supported with an encrypted bitstream in the LX, SX, and FX12 devices” as last
paragraph in “Loading the Encryption Key,” page 24 and as last line in first paragraph
in “Bitstream Encryption and Internal Configuration Access Port (ICAP),” page 25.
Added third paragraph to “Loading Encrypted Bitstreams,” page 24. Clarified
SelectMAP Data Pin Description in Table 2-4, page 39. Added port width to “SelectMAP
Reconfiguration,” page 51. Added first paragraph to Chapter 4, “Frame ECC Logic,”
page 75. Updated the BitGen option to DONE_CYCLE:KEEP in Chapter 5, “User Access
Register,” page 77. Added “Frame Address Register (FAR),” page 92. Corrected
Configuration Data in Table 8-2, page 103 (step 4 and step 6). Changed DESYCH to
DESYNC (throughout).
01/12/07 1.5 Updated notes relevant to Figure 2-5. Updated Table 2-4, Table 3-3, and the “Instruction
Register” section. Added the “ICAP - Internal Configuration Access Port” section.
Updated the “Control Register (CTL)” section, Table 7-7, and Figure 8-2.
06/21/07 1.6 Updated “Introduction,”Table 1-2, “Master Serial Configuration,” “SelectMAP Data
Loading,” Chapter 5, “User Access Register,” “Changing the Multiply and Divide
Values,” “Dynamic Phase Shifting Through the DRP in Direct Mode,” Table 7-1, CBC
address value in Table 7-5, “Configuration Memory Read Procedure (SelectMAP),” and
Table 8-2. Added
“Packet Types”section.
07/30/07 1.7 Added TAP controller state definitions in the “TAP Controller” section and a NOOP note
to Table 8-1.
08/08/07 1.8 Replaced instructions for setting a direct phase shift value in the “Dynamic Phase
Shifting Through the DRP in Direct Mode” section.
10/01/07 1.9 Title: Updated corporate disclaimer.
Chapter 2: Updated notes relevant to Figure 2-3 and updated Figure 2-19.
Chapter 3: Updated “TAP Controller” section.
Chapter 8: Updated Table 8-5.
04/08/08 1.10 Chapter 1: Updated Table 1-6 and “Loading Encrypted Bitstreams” section.
Chapter 3: Updated “Identification Register” section, including Table 3-4 and Table 3-5.
06/09/09 1.11 Chapter 1:
• Interchanged phase events 5 and 6 in Table 1-9.
Chapter 2:
• Added cross reference to the Virtex-4 FPGA Data Sheet.
• Changed default oscillator frequency to 4 MHz in Note 3 following Figure 2-4.
• Updated “Single Device SelectMAP Configuration” section.
Chapter 8:
• Updated description of .rba and .rbb files in “Verifying Readback Data” section.
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