7 Host Interface Port
7 – 2
7.2 HIP PIN
SUMMARY
The HIP consists of 27 pins. As shown in Table 7.1, 16 of these are data
pins and 11 are control pins. Some of the control pins have dual functions,
allowing the processor to support different bus protocols.
Pin Number
Name of Pins Direction Function
H
SEL 1 Input HIP Select
HACK 1 Output HIP Acknowledge
HSIZE 1 Input HIP 8/16 Bit Host
0=16-bit; 1=8-bit
BMODE 1 Input HIP Boot Mode Select
0=normal (EPROM); 1=HIP
HMD0 1 Input HIP Bus Strobe Select
0=R
D, WR; 1=RW, DS
HRD/HRW
*
1 Input HIP Read Strobe/
Read/Write Select
HWR/HDS
*
1 Input HIP Write Strobe/
Host Data Strobe
HMD1 1 Input HIP Address/Data Mode
0=separate; 1=multiplexed
HD15-0/HAD15-0
**
16 Bidirectional HIP Data/Address & Data
HA2 /ALE
**
1 Input HIP Host Address 2/
Address Latch Enable
HA1-0/no function
**
2 Input Host Addresses 1 & 0
TOTAL 27
*
HMD0 selects function
**
HMD1 selects function
Table 7.1 Host Interface Port Pins