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Syntax: DM ( I0 , M0 ) = dreg , <ALU> ;
I1 M1 <MAC>
I2 M2 <SHIFT>
I3 M3
I4 M4
I5 M5
I6 M6
I7 M7
PM ( I4 , M4 )
I5 M5
I6 M6
I7 M7
Permissible dregs
AX0 MX0 SI
AX1 MX1 SE
AY0 MY0 SR0
AY1 MY1 SR1
AR MR0
MR1
MR2
Description: Perform the designated arithmetic operation and data
transfer. The write operation moves the contents of the source to the
specified memory location. The addressing mode when combining an
arithmetic operation with a memory write is register indirect with post-
modify. For linear (i.e. non-circular) indirect addressing, the L register
corresponding to the I register used must be set to zero. The contents of
the source are always right-justified in the destination register.
The computation must be unconditional. All ALU, MAC and Shifter
operations are permitted except Shift Immediate and ALU DIVS and
DIVQ instructions.
The fundamental principle governing multifunction instructions is that
registers (and memory) are read at the beginning of the processor cycle
and written at the end of the cycle. The normal left-to-right order of
clauses (memory write first, computation second) is intended to imply
this. In fact, you may code this instruction with the order of clauses
reversed. The assembler produces a warning, but the results are identical
at the opcode level. If you turn off semantics checking in the assembler (–s
switch) the warning is not issued.
MULTIFUNCTION
COMPUTATION with MEMORY WRITE
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