15
15 – 100
Because of the read-first, write-second characteristic of the processor,
using the same register as destination in one clause and a source in the
other is legal. The register supplies the value present at the beginning of
the cycle and is written with the new value at the end of the cycle.
For example,
(1) DM (I0, M0) = AR, AR = AX0 + AY0;
is a legal version of this multifunction instruction and is not flagged by the
assembler. Reversing the order of clauses, as in
(2) AR = AX0 + AY0, DM (I0, M0) = AR;
results in an assembler warning, but assembles and executes exactly as the
first form of the instruction. Note that reading example (2) from left to
right may suggest that the result of the computation in AR is then written
to memory, all in the same cycle. In fact, this is not possible. The left-to-
right logic of example (1) suggests the operation of the instruction more
closely. Regardless of the apparent logic of reading the instruction from
left to right, the read-first, write-second operation of the processor
determines what actually happens.
Status Generated: All status bits are affected in the same way as for the
single function versions of the selected arithmetic operation.
<ALU> operation
ASTAT: 7 6 543210
SS MV AQ AS AC AV AN AZ
---*****
AZ Set if result equals zero. Cleared otherwise.
AN Set if result is negative. Cleared otherwise.
AV Set if an overflow is generated. Cleared otherwise.
AC Set if a carry is generated. Cleared otherwise.
AS Affected only when executing the Absolute Value operation
(ABS). Set if the source operand is negative.
MULTIFUNCTION
COMPUTATION with MEMORY WRITE
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