EControl/Status Registers
E – 5
Default bit values at reset are shown; if no value is shown, the bit is undefined at reset.
Reserved bits are shown on a gray field—these bits should always be written with zeros.
SPORT0 Autobuffer Control Register
(Not on ADSP-2105)
DM(0x3FF3)
1514131211109876543210
TBUF
Transmit Autobuffering Enable
0 000
RBUF
Receive Autobuffering Enable
TIREG TMREG RIREG RMREG
00
BIASRND
MAC Biased Rounding Control Bit
(ADSP-2171, ADSP-2181, ADSP-21msp58/59 only)
CLKODIS
CLKOUT Disable Control Bit
(ADSP-2171, ADSP-2181, ADSP-21msp58/59 only)
Memory-Mapped Registers
SPORT0 SCLKDIV
Serial Clock Divide Modulus
1514131211109876543210
1514131211109876543210
SPORT0 RFSDIV
Receive Frame Sync Divide Modulus
DM(0x3FF4)
DM(0x3FF5)
SCLK frequency
RFS frequency
RFSDIV = – 1SCLKDIV = – 1
CLKOUT frequency
2
*
(SCLK frequency)
(Not on ADSP-2105)
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