Analog Devices adsp-2100

Contents
viii
CHAPTER 9 SYSTEM INTERFACE
9.1 OVERVIEW ........................................................................................ 9–1
9.2 CLOCK SIGNALS.............................................................................. 9–3
9.2.1 Synchronization Delay................................................................ 9–3
9.2.2 1x & 1/2x Clock Considerations ............................................... 9–4
9.3 RESET ........................................................................................ 9–4
9.4 SOFTWARE-FORCED REBOOTING ............................................. 9–4
9.4.1 ADSP-2181 Register Values For BDMA Booting .................. 9–13
9.5 EXTERNAL INTERRUPTS............................................................. 9–14
9.5.1 Interrupt Sensitivity .................................................................. 9–14
9.6 FLAG PINS ...................................................................................... 9–15
9.7 POWERDOWN ................................................................................ 9–17
9.7.1 Powerdown Control .................................................................. 9–18
9.7.2 Entering Powerdown ................................................................ 9–19
9.7.3 Exiting Powerdown................................................................... 9–20
9.7.3.1 Ending Powerdown With The
PWD Pin.......................... 9–20
9.7.3.2 Ending Powerdown With The
RESET Pin ....................... 9–21
9.7.4 Startup Time After Powerdown .............................................. 9–21
9.7.4.1 Systems Using An External TTL/CMOS Clock .............. 9–21
9.7.4.2 Systems Using A Crystal/Internal Oscillator.................. 9–22
9.7.5 Operation During Powerdown................................................ 9–23
9.7.5.1 Interrupts & Flags ................................................................ 9–23
9.7.5.2 SPORTS ................................................................................. 9–23
9.7.5.3 HIP During Powerdown..................................................... 9–24
9.7.5.4 IDMA Port During Powerdown (ADSP-2181) ................ 9–25
9.7.5.5 BDMA Port During Powerdown (ADSP-2181) ............... 9–26
9.7.5.6 Analog Interface (ADSP-21msp5x) ................................... 9–26
9.7.6 Conditions For Lowest Power Consumption ........................ 9–26
9.7.7 PWDACK Pin ............................................................................. 9–29
9.7.8 Using Powerdown As A Non-Maskable Interrupt............... 9–30
CHAPTER 10 MEMORY INTERFACE
10.1 OVERVIEW ...................................................................................... 10–1
10.2 PROGRAM MEMORY INTERFACE ............................................ 10–3
10.2.1 External Program Memory Read/Write ................................ 10–3
10.2.2 Program Memory Maps............................................................ 10–5
10.2.3 ROM Program Memory Maps ................................................. 10–6
10.3 DATA MEMORY INTERFACE ................................................... 10–10
10.3.1 External Data Memory Read/Write ..................................... 10–10
10.3.2 Data Memory Maps................................................................. 10–11
10.3.3 Memory-Mapped Peripherals................................................ 10–14