Contents
vii
CHAPTER 7 HOST INTERFACE PORT
7.1 OVERVIEW ........................................................................................ 7–1
7.2 HIP PIN SUMMARY......................................................................... 7–2
7.3 HIP FUNCTIONAL DESCRIPTION............................................... 7–4
7.4 HIP OPERATION .............................................................................. 7–6
7.4.1 Polled Operation .......................................................................... 7–7
7.4.1.1 HIP Status Synchronization ................................................. 7–8
7.4.2 Interrupt-Driven Operation ....................................................... 7–9
7.4.3 HDR Overwrite Mode................................................................. 7–9
7.4.4 Software Reset ............................................................................ 7–10
7.5 HIP INTERRUPTS ........................................................................... 7–10
7.6 HOST INTERFACE TIMING ......................................................... 7–11
7.7 BOOT LOADING THROUGH THE HIP ..................................... 7–16
CHAPTER 8 ANALOG INTERFACE
8.1 OVERVIEW ........................................................................................ 8–1
8.2 A/D CONVERSION ......................................................................... 8–2
8.2.1 Analog Input ................................................................................ 8–2
8.2.2 ADC ........................................................................................ 8–3
8.2.2.1 Decimation Filter ................................................................... 8–4
8.2.2.2 High Pass Filter ...................................................................... 8–5
8.3 D/A CONVERSION ......................................................................... 8–6
8.3.1 DAC ........................................................................................ 8–6
8.3.1.1 High Pass Filter ...................................................................... 8–6
8.3.1.2 Interpolation Filter................................................................. 8–7
8.3.1.3 Analog Smoothing Filter & Programmable Gain Amp. .. 8–8
8.3.2 Differential Output Amplifier.................................................... 8–8
8.4 OPERATING THE ANALOG INTERFACE .................................. 8–9
8.4.1 Memory-Mapped Control Registers ......................................... 8–9
8.4.1.1 Analog Control Register ....................................................... 8–9
8.4.1.2 Analog Autobuffer/Powerdown Register....................... 8–10
8.4.2 Memory-Mapped Data Registers ............................................ 8–11
8.4.3 ADC & DAC Interrupts ............................................................ 8–12
8.4.3.1 Autobuffering Disabled ...................................................... 8–12
8.4.3.2 Autobuffering Enabled ....................................................... 8–13
8.5 CIRCUIT DESIGN CONSIDERATIONS...................................... 8–16
8.5.1 Analog Signal Input .................................................................. 8–16
8.5.2 Analog Signal Output ............................................................... 8–18
8.5.3 Voltage Reference Filter Capacitance ..................................... 8–19
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