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Display Adapter Controls (continued)
The video pattern
of
7 possible data bits followed by a
a bit is stored in the 2048 x 16 display ROS
as
8-bit
horizontal rows
of
the characters
to
be displayed. The
8-bit
rows are read (along
with
two
a-bit
spacer bits)
into the
10-bit
shift
register each time the character
counter is advanced. The address
of
each
8-bit
horizontal
row
is derived from the data in the display
data register, which selects the character pattern, and
from the
row
counter, which selects the horizontal
row
of
the character pattern.
When
the electron beam begins
to
scan the upper
left
corner
of
the display screen, the character, line, and
row
counters are all set
to
zero. The storage address bus
contains information from the character counter, the line
counter, the DISPLAY REGISTERS switch, and the
L32-64-R32
switch.
The
first
two
bytes
of
data are read
from
read/write
storage into the display data register. Because the
two
counters are 0, the even byte in the display data register
is used
to
read the first
8-bit
horizontal
row
from
the
2048 x 16 display
ROS
into the
10-bit
register. The 10
bits from the register are shifted
out
serially as video
pulses, and the character counter is advanced.
The odd byte in the display data register is used to
address the next character pattern. The
top
row
of
this
pattern is
put
into the
10-bit
shift
register and shifted
out. The character counter is advanced again; because
it
now
contains
an
even number, the next
two
bytes in
read/write
storage are read into the display data
register. This process continues until all
64
characters in
the
top
row
are accessed. Then the character counter
returns
to
0, the address bus returns
to
the base
address, and the row counter becomes
1.
The entire
process is repeated
for
the
first
line
of
characters in the
second row.
After
the
row
counter reaches 12,
it
is reset
to
0, and
the line counter is advanced. The line counter increment
adds
64
to
the base address so
that
the next
64
characters in
read/write
storage are accessed.
The preceding process continues
for
each line. One is
added
to
the
row
counter each time the character
counter reaches 64, and one is added
to
the line counter
each time the
row
counter reaches 12.
When
the line
counter reaches 16, the
row
counter reaches 12, and the
characters counter reaches 64, the frame is completed.
The counters continue advancing
to
maintain
synchronization while the beam retraces
from
the lower
right
to
the upper
left
of
the display screen. The
counters are then reset
to
zero, and the next frame
begins.
The previous discussion applies when the DISPLAY
REGISTERS switch is set
to
the NORMAL position and
the
L32-64-R32
switch is set
to
64, although the
differences
for
other settings is slight.
When
the
DISPLAY REGISTERS switch is set
to
the DISPLAY
REGISTERS position, the first hexadecimal
digit
of
the
byte is shown on line
1,
and the second hexadecimal
digit is shown on line
2.
Therefore, the base address is
advanced only on even lines.
The
first
4 bits
of
each byte in the display data register
are used
to
address the character pattern on the odd
numbered lines; the second 4 bits
of
each byte are used
to
address the character pattern on the even numbered
lines.
When
the
L32-64-R32
switch is set
to
either L32 or
R32, a blank character is inserted between
the
characters so
that
only the 32
leftmost
or the 32
rightmost characters are displayed. To accomplish this,
the sequential bytes are read
from
read/write
storage
on every fourth count
of
the character counter, rather
than on every second count. The
shift
register loads
every other count and produces the blanks between
characters.
Display
447
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