Display Unit
I/O
Lines
When
black characters are displayed on a
white
background, the character video signal is sent
to
the
cathode
of
the
CRT.
This signal blanks the beam
everywhere character information appears on the display
screen. Therefore,
if
no video signal is sent
to
the
display unit, the display is completely white.
When
white characters are displayed on a black
background, the '+machine video' line blanks the beam
everywhere except where a character appears.
Therefore,
if
no video signal is
sent
to
the display unit,
the display is completely dark.
The'
-external vertical sync' line goes directly
to
the
display
PC
board; this signal keeps the video signal
synchronized
with
the vertical and horizontal signals.
If
the'
-external vertical sync' signal is missing, the video
information rolls vertically.
The '+external horizontal sync' line controls the beam
sweeping horizontally across the display.
If
the
'+external horizontal sync' is missing, the display is
black.
Cycle Steal Control Lines
The display adapter and the controller access
read/write
storage through the storage read bus. The cycle steal
control lines control the
way
in
which the adapter and
the controller use the storage read bus and the storage
access cycles.
The'
-display
request' line is used
by
the display
adapter
to
request a storage cycle steal when the
adapter is ready
to
receive the next
two
bytes
of
data
in
the display data register. The controller activates the
'-stolen
cycle next' line during the storage cycle that
precedes the requested stolen cycle.
The'
-stolen cycle
next' signal deactivates the
'-display
request' line and
limits the display adapter
to
alternating
the
cycle steal
activity
with
a controller storage cycle.
During the stolen storage cycle, the controller activates
the'
-stolen
cycle' line and puts the
two
types
of
data
addressed by the storage address bus onto the storage
read/write
bus.
The'
-stolen cycle' line also gates the
data from the storage read bus into the display register
on the display card.
448
Microinstructions are processed faster when no storage
cycles are stolen. The
I/O
display offline is set
or
reset
by
a microinstruction
to
prevent cycle steal activity by
the display. When cycle steal activity is prevented, the
display is blank and the IN PROCESS light is on.
Read/Write Storage
I/O
Lines
The
I/O
lines from the display card
to
read/write
storage consist
of
the storage read bus (input
linesland
the storage address bus (output lines). See the
ControJler Data Flow diagram in this section.
The storage address bus on the display card is sent a
base address (CRT buffer address); this address is
determined
by
the position
of
the DISPLAY REGISTERS
switch (DISPLAY REGISTERS
or
NORMAL
position).
When
the switch is
in
the DISPLAY REGISTERS
position, the base address is 0000, and the contents
of
addresses 0000-01
FF
are displayed. (See Display
Registers
in the Diagnostic Aids section and ControJler in
this section
for
the contents
of
these addresses.) When
the switch is
in
the NORMAL position, the base address
is 0200, and the contents
of
addresses
0200-05FF
in
read/write
storage are displayed.
After
the base address is set, the character counter
updates the addresses by
two
(the
low
order bit is
always logical
0)
every other character count
(CC1
time).
For each address received from the display card,
two
bytes
of
data are transferred from the storage
read/write
bus
to
the display card.
If
the
L32-64-R32
switch is set
to
L32
or
R32, the
character counter updates the address every fourth
character count. The address lines cause
read/write
storage
to
gate the information
from
the addressed
storage positions
to
the storage read bus and into the
display data register.
The data is transferred
to
the display adapter through
the storage read bus. This data is double buffered by
the display data register and the character register. The
data is gated into the display data register when clock
lines
'MCC3'
and
'MCC4'
and the
'-stolen
cycle' line are
active. The
'+C4
powered' and
'+C5
powered' lines are
used
to
synchronize the data into the character register.
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