Intel 855GME - Page 305

January 2007 305
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Layout Checklist
COMP[0,2]
• Terminate each signal to ground with 27.4
Ω
±1% resistors.
• Connect each to CPU with a Zo = 27.4
Ω
trace that is less than 0.5 inches from the
pin.
• Spacing from other switching signal traces
should be a minimum of 25 mils.
•Refer to Section 4.1.9.1 for
detailed layout recommendations.
COMP[1,3]
• Terminate each signal to ground with 54.9
Ω
±1% resistors.
• Connect each to CPU with a Zo = 55
Ω trace
that is less than 0.5 inches from the pin.
• Spacing from other switching signal traces
should be a minimum of 25 mils.
•Refer to Section 4.1.9.1 for
detailed layout recommendations.
Processor Power and GND Measurement/Sense Signals
VCCSENSE
VSSSENSE
• Route traces of equal length using 3:1
spacing, Zo = 55
Ω ± 15%.
• Place via next to the processor socket’s pin
for measurement of CPU_VCC/VSS.
• Place a ground via 100 mils from each test
point via.
• All other signals shall be a minimum of 25
mils (preferably 50 mils) from VCCSENSE
and VSSSENSE routing.
•Refer to Section 4.1.11 for more
information.
Processor Decoupling, VREF, and Filtering
GTLREF
• Connect CPU GTLREF pin to a 1 K
Ω ±1%
and 2 K
Ω ± 1% resistive divider to VCCP.
• No decoupling on this signal.
• Connect voltage divider node to CPU
GTLREF pin with a Zo = 55
Ω trace that is
shorter than 0.5 inches
• Minimum separation from other switching
signals should be 25 mils.
•Refer to Section 4.1.8 for more
information.
Table 148. Processor Layout Checklist (Sheet 6 of 7)
Checklist Items Recommendations Comments