Revision:1.0(2023-01-12)
411
Verify whether the PCIe bus between the PC module and the FPGA is normal.
• Test Items
The full-space read/write test is conducted for the DDR mounted to the MF FPGA.
• Test failure analysis
If the test result is Error, the drive is abnormal.
If the test result is FAIL, the connections between the FPGA and the mounted DDRs are
abnormal.
• Troubleshooting suggestion
1. If the test result is Error, restart the device and re-perform the self-test. If the problem persists,
restore the device.
2. If the test result is FAIL, replace the main board.
Z0202 AFE Test Mode Test
• Upper-level test item
Communication Test Between PC Module and MF FPGA
• Test Items
Enter the system test mode, write data to AFE globally, and write the delay RAM. Read the
data from the channel delay storage and locate the specific channel and AFE chip.
• Test failure analysis
If the test result is Error, the drive is abnormal.
If the test result is FAIL, the AFE chip has an error.
• Troubleshooting suggestion
1. If the test result is Error, restart the device and re-perform the self-test. If the problem persists,
restore the device.
2. If the test result is FAIL, perform the self-test again. If the test result is still FAIL, replace the
main board.
Z0203 EC ARM Communication Test
• Upper-level test item
Communication Test Between PC Module and MF FPGA
• Test Items
Test whether the communication serial port UART between the EC ARM and the FPGA is
normal. Read the firmware version and firmware compilation time.
• Test failure analysis
If the test result is Error, the drive is abnormal.
If the test result is FAIL, the serial ports of the EC ARM and the MF FPGA are faulty.
• Troubleshooting suggestion
1. If the test result is Error, the logic of the MF FPGA is wrong. In this case, restart the device and
re-perform the self-test. If the fault persists, recover the device.
Diagnostic Ultrasound System
Service Manual
9 Appendix
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