Motorola MC68HC908AB32 User Manual

Central Processor Unit (CPU)
Technical Data MC68HC908AB32 — Rev. 1.0
104 Central Processor Unit (CPU) MOTOROLA
ROR opr
RORA
RORX
ROR opr ,X
ROR ,X
ROR opr ,SP
Rotate Right through Carry ↕ ––↕↕↕
DIR
INH
INH
IX1
IX
SP1
36
46
56
66
76
9E66
dd
ff
ff
4
1
1
4
3
5
RSP Reset Stack Pointer SP ← $FF ––––––INH 9C 1
RTI Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
↕↕↕↕↕↕INH 80 7
RTS Return from Subroutine
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
––––––INH 81 4
SBC # opr
SBC opr
SBC opr
SBC opr ,X
SBC opr ,X
SBC ,X
SBC opr ,SP
SBC opr ,SP
Subtract with Carry A ← (A) – (M) – (C) ↕ ––↕↕↕
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A2
B2
C2
D2
E2
F2
9EE2
9ED2
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
SEC Set Carry Bit C ← 1 –––––1INH 99 1
SEI Set Interrupt Mask I ← 1 ––1–––INH 9B 2
STA
opr
STA opr
STA opr ,X
STA opr ,X
STA ,X
STA opr ,SP
STA opr ,SP
Store A in M M ← (A) 0 – – ↕↕–
DIR
EXT
IX2
IX1
IX
SP1
SP2
B7
C7
D7
E7
F7
9EE7
9ED7
dd
hh ll
ee ff
ff
ff
ee ff
3
4
4
3
2
4
5
STHX opr Store H:X in M (M:M + 1) ← (H:X) 0 – – ↕↕– DIR 35 dd 4
STOP Enable IRQ Pin; Stop Oscillator I ← 0; Stop Oscillator ––0–––INH 8E 1
STX opr
STX opr
STX opr ,X
STX opr ,X
STX ,X
STX opr ,SP
STX opr ,SP
Store X in M M ← (X) 0 – – ↕↕–
DIR
EXT
IX2
IX1
IX
SP1
SP2
BF
CF
DF
EF
FF
9EEF
9EDF
dd
hh ll
ee ff
ff
ff
ee ff
3
4
4
3
2
4
5
Table 7-1. Instruction Set Summary (Continued)
Source
Form
Operation Description
Effect on
CCR
Address Mode Opcode Operand Cycles
VHINZC
b0
b7
C

Motorola MC68HC908AB32 Specifications

General

Brand	Motorola
Model	MC68HC908AB32
Category	Controller
Language	English