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General| Brand | Panasonic |
|---|---|
| Model | MN101L Series |
| Category | Computer Hardware |
| Language | English |
Details the hardware features of the MN101LR05D LSI, including CPU core, memory, and clock oscillators.
Compares the specifications of MN101LR05D, MN101LR04D, MN101LR03D, and MN101LR02D.
Provides a detailed description of each pin's function and configuration for various MN101L series devices.
Details electrical specifications including absolute maximum ratings, operating conditions, and DC characteristics.
Illustrates the physical dimensions and package codes for the MN101LR05D, MN101LR04D, MN101LR03D, and MN101LR02D.
Provides essential guidelines and precautions for setting up circuits, including usage notes and handling of unused pins.
Provides a high-level overview of the AM13L core (CPU), its basic specifications, and architecture.
Details the bus interface of the CPU, including the bus controller, access cycles, and control registers.
Explains the extended calculation functions available, such as multiplication, division, and BCD operations.
Describes the extended calculation instructions, including their formats, operations, and PSW bit changes.
Details the reset function, including reset factors, sequences, and oscillation stabilization wait time.
Provides an overview of the interrupt services, including NMI and maskable interrupts, priority levels, and acceptance procedures.
Lists and describes the interrupt control registers, including those for external, group, and other interrupts.
Details the functions and configurations of external interrupts, including trigger edges, noise filters, and key inputs.
Explains the clock oscillation circuits and control registers for managing system and peripheral clocks.
Describes the LSI's operating modes (NORMAL, SLOW, HALT, STOP, IDLE) and mode transition procedures.
Details the power supply voltage options (1.1V, 1.3V, 1.8V) and their relation to operating frequency and mode.
Illustrates the state transitions based on changes in operation mode, VDD18 voltage, and clock.
Introduces the watchdog timer function, its interrupt generation, and reset behavior.
Details the WDT control register (WDCTR), including clock source selection and error detect period setup.
Explains the operation of the watchdog timer, including counter clearing and WDIRQ generation.
Describes the power supply voltage detector (PSVD) function, its interrupt generation, and operating conditions.
Lists and details the PSVD related control registers (LVICTR0, LVICTR1, LVICTR2).
Provides a setting example for PSVD operation, demonstrating CPU transition from STOP to NORMAL mode.
Provides an overview of I/O ports, listing the registers used for control and the status at reset.
Details the I/O port control registers, including output, input, direction, pull-up, and open-drain controls.
Describes the general purpose port functions and special functions assigned to each port.
Details the special functions of Port 0 and its setup procedures.
Details the special functions of Port 1 and its setup procedures.
Details the special functions of Port 2 and its setup procedures.
Details the special functions of Port 3 and its setup procedures.
Details the special functions of Port 4 and its setup procedures.
Details the special functions of Port 5 and its setup procedures.
Details the special functions of Port 6 and its setup procedures.
Details the special functions of Port 7 and its setup procedures.
Details the special functions of Port 8 and its setup procedures.
Provides an overview of the six 8-bit timers, detailing their functions and pin assignments.
Lists and describes the registers for controlling the 8-bit timers, including prescaler, programmable, and mode registers.
Explains the operation and setup of the 8-bit timers, including count timing and interrupt generation.
Details the operation and setup for the 8-bit event count function using external inputs.
Explains the operation and setup of the 8-bit timer pulse output function.
Describes the operation and setup for 8-bit PWM output, including additional pulses.
Explains the operation and setup for simple pulse width measurement using external interrupt pins.
Details the operation and setup for cascading 8-bit timers to create 16-bit timers.
Provides an overview of the 16-bit timers (Timer 7, 8, 9), listing their functions and I/O pins.
Lists and describes the registers for controlling the 16-bit timers, including binary counters, compare registers, and mode registers.
Explains the operation and setup of the 16-bit timers, including count timing and interrupt generation.
Details the operation and setup for the 16-bit event count function using TMnIO input.
Explains the operation and setup of the 16-bit timer pulse output function.
Describes the operation and setup for standard PWM output with variable duty cycle.
Details the operation and setup for high-precision PWM output with variable period and duty.
Explains the operation and setup of the 16-bit timer capture function using external interrupts or timer interrupts.
Describes the operation and setup for standard IGBT output with variable duty.
Details the operation and setup for high-precision IGBT output with variable period and duty.
Explains the operation and setup for IGBT output with dead time.
Introduces the time base timer and the 8-bit free-running timer (timer 6).
Lists and describes the registers for controlling Timer 6 and the time base timer.
Explains the operation and clock sources for the 8-bit free-running timer (Timer 6).
Describes the operation and setup for the time base timer, including interrupt generation cycles.
Provides an overview of the RTC time base timer (RTC-TBT) and its functions.
Lists and describes the registers for controlling the RTC-TBT.
Explains the operation of the RTC-TBT, including counting, interrupt generation, and data writing.
Provides an overview of the Real Time Clock (RTC) functions, including clock source and time display.
Lists and describes the registers for controlling the RTC, including control, alarm, periodic interrupt, and clock registers.
Explains the operation of the RTC, including periodic and alarm interrupts, and clock data reading procedures.
Introduces the four serial interfaces (SCIF0-3) and their communication types.
Details the control registers for SCIFn and BRTMn, including mode, status, and pin control registers.
Describes the clock-synchronous communication modes (2-wire, 3-wire, 4-wire) and timing.
Details the full-duplex UART communication, including forms, operations, and setting procedures.
Explains IIC communication format, operation, timing, and setup examples.
Introduces the Direct Memory Access Controller (DMA) and its features.
Lists and describes the DMA control registers, including control, source address, destination address, and transfer word count registers.
Explains the DMA data transfer modes: single transfer and burst transfer.
Provides an overview of the buzzer circuit, its functions, and block diagram.
Lists and describes the Buzzer Control Registers.
Explains the operation of the buzzer circuit, including output frequency and pin control.
Introduces the Analog-to-Digital Converter (ADC) with 12-bit resolution and its functions.
Lists and describes the ADC control registers and data storage buffers.
Details the operation of the ADC circuit, including setting procedures and cautions.
Provides an overview of the LCD driver circuit (LCDDRV), including segment/common pins and functions.
Lists and describes the LCD control registers for mode, output, and display selection.
Explains the operation of the LCD driver (LCDDRV), voltage booster, and reference voltage circuits.
Shows examples of LCD display configurations and operations in static, 1/2, 1/3, and 1/4 duty modes.
Provides an overview of ReRAM specifications, including memory size, endurance, and voltage.
Details the self-programming method for ReRAM data programming using software libraries.
Lists and describes the registers for controlling ReRAM rewriting and data protection.
Lists the command libraries available for ReRAM rewriting operations.
Introduces the on-board chip debugger (OCD) for program development and data writing to ReRAM.
Provides a comprehensive list of supported on-board debugging functions.
Lists and defines symbols used in the instruction specifications.
Provides a detailed list of MN101L series instructions, including operation, flags, code, and execution cycles.
Presents an instruction map for the MN101L series, detailing opcode mappings.
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