Chapter 10
General-Purpose Time Base/Free-Running Timer
X - 8 8-bit Free-running Timer
10.3 8-bit Free-running Timer
10.3.1 Operation
8-bit Free-running Timer (Timer 6)
The generation cycle of the timer interrupt should be set in advance by selecting the clock source and setting the
compare register (TM6OC). When the binary counter (TM6BC) reaches the setting value of the compare register,
an interrupt request is generated at the next count clock and the binary counter is cleared to restart counting up
from 0x00.
Table:10.3.1 shows selectable clock sources.
Table:10.3.1 Clock Source at Timer Operation (Timer 6)
..
When SCLK is used as the clock source, the timer counts at "falling edge" of the count clock.
When other clock is used, it counts "rising edge" of the count clock.
..
Clock source
One count time
At f
HCLK
= 8 MHz At f
HCLK
= 4 MHz At f
HCLK
= 2 MHz
HCLK 125 ns 250 ns 500 ns
SCLK 30.5 µs
SYSCLK 250 ns 500 ns 1000 ns
HCLK/2
7
16 µs 32 µs64 µs
HCLK/2
13
1024 µs 2048 µs 4096 µs
SCLK/2
7
3.9 ms
SCLK/2
13
250 ms
f
HCLK
= 8 MHz, 4 MHz, 2 MHz
f
SCLK
= 32.768 kHz
f
SYSCLK
= f
HCLK
/2
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