Panasonic MN101L Series

Chapter 4
Clock/ Mode/ Voltage Control
IV - 2 Clock Control
4.1 Clock Control
The LSI has 4 types of clock oscillation circuits.
Table:4.1.1 Clock Oscillation Circuits
Figure:4.1.1 Block Diagram of Clock Control
..
After reset, the LSI operates in SLOW mode where SYSCLK is equal to SRCCLK.
..
..
To lower the LSI power consumption, the clock supply to the peripheral circuits can be con-
trolled with the PRICKCNT0/1/2 registers.
For example, if Timer 0 is not used, the clock supply to Timer 0 is stopped by setting the
PRICKCNT0.PRICKCNT00 to "0".
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Internal high-speed oscillation circuit Max. 10 MHz clock (HRCCLK) can be generated.
External high-speed oscillation circuit
High-speed clock is generated by connecting crystal or ceramic oscillator
to OSC1/OSC2 pins.
Internal low-speed oscillation circuit 40 kHz clock (SRCCLK) can be generated.
External low-speed oscillation circuit
Low-speed clock is generated by connecting crystal oscillator to XI/XO
pins.
M
U
X
M
U
X
HCLK
(High-speed Clock)
SYSCLK (*)
(System Clock)
HSCLK
HSCLK
Divider
External
High-speed
Oscillation
HOSCCLK
Internal
High-speed
Oscillation
HRCCLK
OSC1
OSC2
External
Low-speed
Oscillation
XI
XO
Internal
Low-speed
Oscillation
SRCCLK
M
U
X
SOSCCLK
1/2
Divider
OSCSTBCLK
(Oscillation Stabilization Cloc
k)
SCLK
(Low-speed Clock)
SCLKCNT.SCLKSEL
HCLKCNT.HCLKSEL
CPUM.CLKSEL
* CKCTR.OSCSEL2-0 control the divider ratio of SYSCLK.
SCLKCNT.SRCCNT
CPUM.XIMOD
Operation Enable
CPUM.STOP
S
CLKCNT.SOSCCNT
CPUM.XIMOD
CPUM.STOP
Operation Enable
HCLKCNT.HRCCNT
CPUM.OSCMOD
Operation Enable
CPUM.STOP
HCLKCNT.HOSCCNT
CPUM.OSCMOD
CPUM.STOP
Operation Enable