Panasonic MN101L Series

Chapter 8
8-bit Timer
8-bit Timer VIII - 15
8.3 8-bit Timer
8.3.1 Operation
In the 8-bit timer operation, the timer can generate interrupts periodically.
 8-bit Timer Operation (Timer 0 to Timer 5)
The interrupt generation cycle of the timer is determined by selecting the clock source and setting the value of
TMnOC, in advance. When the value of TMnBC matches the setting value of timer n compare register, an inter-
rupt request is generated at the next count clock. Then, the timer n binary counter is cleared and restarts counting
up from "0x00".
The clock source can be selected depending on timers as shown in the table below.
..
When using SCLK as a clock source, the timer counts at the falling edge of the count clock.
When using other clocks, the timer counts at the rising edge of the count clock.
..
Clock source Time per Count Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5
HCLK 100 ns √√√√√√
HCLK/4 400 ns √√√√√√
HCLK/16
1.6 µs
√√√√√√
HCLK/32 3.2 µs √ - √ - √ -
HCLK/64 6.4 µs √√√√√√
HCLK/128 12.8 µs-√ - √ - √
SYSCLK/2 400 ns √√√√√√
SYSCLK/4 800 ns √ - √ - √ -
SYSCLK/8 1600 ns - √ - √ - √
SCLK
30.5 µs
√√√√√√
f
HCLK
=10 MHz, f
SCLK
=32.768 kHz
f
SYSCLK
= HCLK/2 = 5 MHz