Chapter 17
LCD
XVII - 2 Overview
17.1 Overview
This LSI has an LCD driver circuit (LCDDRV) which is composed of 43 segment output pins and 4 common out-
put pins (39 segment output pins and 8 common output pins). The LCDDRV has an LCD reference voltage circuit
(REFVOL) and a voltage booster circuit (BSTVOL).
Table:17.1.1 shows the functions of LCDDRV.
Table:17.1.1 LCD Functions
LCD operations are restricted depending on the CPU mode which is shown in Table:17.1.2.
Table:17.1.2 LCD Function Restrictions in Each CPU Mode
..
The supply voltage to VLC1 (V
LC1
) must be kept between V
DD30
and 3.6 V.
(V
DD30
≤ V
LC1
≤ 3.6 V).
When LCDDRV is not used, Supply V
DD30
to VLC1 pin. At this time, VLC2/VLC3/C1/C2 pins
are used as general-purpose ports.
..
Function Details
Duty
Static
1/2 to 1/8 duty
LCD Power Supply
V
LC1
,V
LC2
, V
LC3
LCD Reference Voltage Circuit (REFVOL) 0.05 V increments within a range of 0.9 V to 1.8 V
LCD Voltage Booster Circuit (BSTVOL) Boosts reference voltage input by 2, 3 times.
Clock Source for LCD Display (LCDCLKS)
SCLK, HCLK/2
4
, HCLK/2
5
, HCLK/2
6
, HCLK/2
7
, HCLK/2
8
LCD Display Clock (LCDCLK)
LCDCLKS/2
3
, LCDCLKS/2
4
, LCDCLKS/2
5
, LCDCLKS/2
6
, LCDCLKS/2
7
, LCD-
CLKS/2
8
, LCDCLKS/2
9
, LCDCLKS/2
10
, LCDCLKS/2
11
, LCDCLKS/2
12
Clock Source for BSTVOL (LCUPCKS)
SCLK, HCLK/2
4
, HCLK/2
5
, HCLK/2
6
, HCLK/2
7
, HCLK/2
8
Boost Clock for BSTVOL (LCUPCK)
LCUPCKS × 1/8, LCUPCKS × 1/16, LCUPCKS × 1/32,
LCUPCKS × 1/64, LCUPCKS × 1/128
LCDCLKS : Selected clock with LCDMD3.LCCKS2-0
LCDCLK : Selected clock with LCDMD3.LCCK3-0
LCUPCKS : Selected clock with LCDMD0.LCUPCKS2-0
LCUPCK : Selected clock with LCDMD0.LCUPCKDIV2-0
CPU Mode
Clock Source for LCDCLKS
Clock Source for LCUPCKS
HCLK-based SCLK-based
Operation Mode
NORMAL
√√
SLOW
- √
Standby Mode
HALT0
∆∆
HALT1
- ∆
HALT2/HALT3
-
∆
STOP0/STOP1
--
√: LCD operation is enabled ∆: Displaying data can be maintained. −: LCD operation is disabled.
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