Panasonic MN101L Series

Chapter 17
LCD
Overview XVII - 3
17.1.1 LCD Driver Circuit Block Diagram
Figure:17.1.1 LCD Driver Circuit Block Diagram
LCDTY0 LCDTY1 LCDTY2
Reserved
LCMODS
LCMOD0
LCEN
LCMOD1
LCDMD2
0
7
LCDMD0.LCUPEN LCDMD0.LCUPCKDIV2-0 LCDMD0.LCUPCKS2-0 LCDMD4.LCUPMD
SEG42 SEG0SEG1COM0COM1COM7
V
SS
C1 C2
V
LC1
V
LC2
V
LC3
3
...............
HCLK
SCLK
LCDATA0LCDATA1LCDATA42
......
888
......
....
LCDMD1.LCVREN LDCMD1.LCVRO4-0
8
LCDMD3.LCCK3-0 LCDMD3.LCCKS2-0
3
MUXMUXMUX
Segment driver
Common driver
Segment output latch
Circuit to
control
display
timings
LCD clock-dividing circuit
Booster circuit
Reference
power
supply circuit
Booster clock
control circuit
HCLK
SCLK