Panasonic MN101L Series

Chapter 14
DMA Controller
Overview XIV - 3
14.1.1 Block Diagram
Figure:14.1.1 Block Diagram
DMCTRnL/H (n=0,1)
DMA control register
..
DMBG0 DMBG1 DMBG2 DMBG3 DMBG4
DMSAM
DMDAM
- - - - - - - - - - - - - -
DMTM
DMUT
-
DMTEN
DMRQF
DMOVF
Access size
Timing
control signal
D
estination address
Whole
control
Source address
DMCNTL/H
Transfer word count register
DMDSTL/M/H
Destination address register
DMSRCL/M/H
Source address register
IRQ7 ( KEY interrupt )
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
IRQ0
Timer 0 interrupt
Timer 2 interrupt
Timer 1 interrupt
Timer 3 interrupt
Timer 4 interrupt
Timer 5 interrupt
Timer 7 interrupt
Timer 7 input capture factor
Timer 8 interrupt
Timer 8 input capture factor
Timer 9 interrupt
Timer 9 input capture factor
Serial interface 0 reception interrupt
Serial interface 0 transmission interrupt
Serial interface 0 buffer empty factor
Serial interface 1 reception interrupt
Serial interface 1 transmission interrupt
Serial interface 2 transmission complete interrupt
Serial interface 1 buffer empty factor
Serial interface 2 buffer empty factor
Serial interface 3 transmission complete interrupt
Serial interface 3 buffer empty factor
A/D conversion interrupt
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