Chapter 14
DMA Controller
DMA Controller Control Registers XIV - 5
14.2.1 DMA Control Register
DMA Control Register 0 lower side (DMCTR0L: 0x03E00)
bp76543210
Bit name DMSAM - - DMBG4-0
At reset00000000
Access R/W R R R/W R/W R/W R/W R/W
bp Bit name Description
7DMSAM
Source Address increment control
0: Enable (Incremented)
1: Disable (Fixed)
6-5 - Always read as "0".
4-0 DMBG4-0
DMA start trigger
00000: software trigger
00001: IRQ0
00010: IRQ1
00011: IRQ2
00100: IRQ3
00101: IRQ4
00110: IRQ5
00111: IRQ6
01000: IRQ7 (KEY interrupt)
01001: Timer 0 interrupt
01010: Timer 1 interrupt
01011: Timer 2 interrupt
01100: Timer 3 interrupt
01101: Timer 4 interrupt
01110: Timer 5 interrupt
01111: Timer 7 interrupt
10000: Timer 7 input capture factor
10001: Timer 8 interrupt
10010: Timer 8 input capture factor
10011: Timer 9 interrupt
10100: Timer 9 input capture factor
10101: Serial interface 0 reception interrupt
10110: Serial interface 0 transmission interrupt
10111: Serial interface 0 buffer empty factor
11000: Serial interface 1 reception interrupt
11001: Serial interface 1 transmission interrupt
11010: Serial interface 1 buffer empty factor
11011: Serial interface 2 transmission complete interrupt
11100: Serial interface 2 buffer empty factor
11101: Serial interface 3 transmission complete interrupt
11110: Serial interface 3 buffer empty factor
11111: A/D conversion interrupt