Panasonic MN101L Series

Chapter 1
Overview
I - 2 Hardware Features
1.1 Hardware Features
MN101LR05D is described in this LSI user's manual.
For MN101LR04D, MN101LR03D and MN101LR02D, refer to [1.2 Comparison of Product Specification] and
[1.3.1 Pin Configuration].
 Features
In this document, the divided clock and the frequency of it are described as follows:
Divided clock: Clock name/n (n: division ratio)
Frequency : f
clock name
•CPU Core
- AM13L core
- LOAD-STORE architecture (3- or 4-stage Pipeline)
• Machine Cycle and Operating Voltage
- High-Speed mode
100 ns / 10 MHz (Max) (V
DD30
: 1.8 V to 3.6 V)
1.0 µs / 1 MHz (Max) (V
DD30
: 1.3 V to 3.6 V)
- Low-Speed Mode
25 µs / 40 kHz (Max) (V
DD30
: 1.1 V to 3.6 V)
• Operating Mode
- NORMAL mode (High-Speed mode)
- SLOW mode (Low-Speed mode)
- HALT mode (High-Speed/Low-Speed mode)
- STOP mode
• Embedded Memory
- ROM (ReRAM) : 64 KB (Programmable area: 62 KB, Data area: 2 KB)
- RAM : 4 KB
• ReRAM Specification
- Program voltage (V
DD30
) : 1.8 V to 3.6 V
- Program cycles : 1 K (Program area), 100 K (Data area)
- Data is rewritable in bytes without data erase.
• Clock Oscillator (4 circuits)
- External Low-Speed Oscillation (SOSCCLK) : 32.768 kHz (crystal or ceramic)
- External High-Speed Oscillation (HOSCCLK): up to 10 MHz (crystal or ceramic)
- Internal Low-Speed Oscillation (SRCCLK) : 40 kHz ± 20 % (V
DD30
: 1.1 V to 3.6 V)
- Internal High-Speed Oscillation (HRCCLK) : 10/8 MHz ± 3 % (V
DD30
: 1.8 V to 3.6 V)
1 MHz ± 10 % (V
DD30
: 1.3 V to 3.6 V)
* MN101LR02D does not have external high-speed oscillation (HOSCCLK).
• Internal Operating Clock
- System Clock (SYSCLK): 10 MHz (Max)
SYSCLK is generated by dividing HCLK or SCLK, and the division ratio is 1, 2, 4, 8, 16 or 32.
HCLK: HOSCCLK or HRCCLK
SCLK: SOSCCLK or SRCCLK
* MN101LR02D cannot be selected HOSCCLK.