Panasonic MN101L Series

Chapter 2
CPU
Extended Calculation Instruction II - 21
2.4.2 MULWU 16-bit x 16-bit multiplication (unsigned)
 Execution of 16-bit × 16-bit multiplication (unsigned)
1. Store the multiplier to DW0 register and the multiplicand to DW1 register.
2. Execute MOV 0x01, (0x03F07) (Extended calculation macro instruction MULWU).
3. The value of the unsigned 16-bit of DW0 register is multiplied by the unsigned 16-bit of DW1 register. Then
the upper 16-bit of the result (32-bit) is stored in DW1 register and the lower 16-bit is stored in DW0 register.
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This extended calculation instruction is generated by the compiler for MN101L series by
appointing an option (-mmuldivw).
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When this extended calculation instruction is executed, the handy address (HA) is updated in
"0x03F07"
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MULWU (MOV 0x01, (0x03F07)) VF NF CF ZF
0
z
0
z
Operation
DW0 * DW1 → {DW1, DW0}
Multiplies the unsigned 16-bit value of DW0 register by the unsigned 16-bit value of
DW1 register, and store the upper 16-bit of the result (32-bit) in the DW1 register and
the lower 16-bit of the result in the DW0 register.
Bit Changes Size, Cycles, Codes
VF: 0
NF: Set if the MSB of the result is "1", otherwise set to "0".
CF: 0
ZF: Set if the result is "0", otherwise set to "0".
6 nibbles
4 cycles
0000 0010 0111 0000 0001 0000