Panasonic MN101L Series

Chapter 8
8-bit Timer
8-bit Timer Control Registers VIII - 5
8.2.1 Timer Prescaler Selection Registers
The timer prescaler selection registers select divided HCLK or SYSCLK as the count clock of 8-bit timer. In addi-
tion, these registers control the function of PWM output with additional pulses for Timer 0, 2 and 4.
 Timer 0 Prescaler Selection Register (CK0MD: 0x03F76)
 Timer 1 Prescaler Selection Register (CK1MD: 0x03F77)
bp76543 210
Bit name - - TM0ADD1-0 TM0ADDEN TM0PSC1-0 TM0BAS
At reset00000 000
Access R R R/W R/W R/W R/W R/W R/W
bp Bit name Description
7 to 6 - Always read as 0.
5 to 4 TM0ADD1-0
Position of additional pulse (within 4 cycles of PWM basic waveform)
00: No pulse
01: At second cycle
10: At first and third cycle
11: At first, second and third cycle
3 TM0ADDEN
PWM output with additional pulses control
0: Disabled (8-bit PWM output)
1: Enabled
2 to 0
TM0PSC1-0
TM0BAS
Clock source select
000: HCLK/4
010: HCLK/16
100: HCLK/32
110: HCLK/64
X01: SYSCLK/2
X11: SYSCLK/4
bp 76543210
Bit name----- TM1PSC1-0TM1BAS
At reset00000000
AccessRRRRRR/WR/WR/W
bp Bit name Description
7 to 3 - Always read as 0.
2 to 0
TM1PSC1-0
TM1BAS
Clock source select
000: HCLK/4
010: HCLK/16
100: HCLK/64
110: HCLK/128
X01: SYSCLK/2
X11: SYSCLK/8