Chapter 2
CPU
Overview II - 3
2.1.1 CPU Control Registers
The LSI allocates the peripheral circuit registers in memory space ("0x03000" to "0x03FFF").
CPU control registers are also allocated in the space.
Table:2.1.2 CPU Control Registers
2.1.2 Data Registers (D0, D1, D2, D3)
Data registers D0 to D3 are 8-bit general-purpose registers.
The four data registers can be paired to form the 16-bit data registers DW0 (D0, D1) and DW1 (D2, D3).
The initial value of Dn is "0x00".
Figure:2.1.1 Data Registers
2.1.3 Address Registers (A0, A1)
These registers are used as address pointers specifying data locations. The initial value of An is "0x0000".
Figure:2.1.2 Address Registers
Symbol Address R/W Register name Pages
CPUM 0x03F00 R/W CPU mode control register IV-4
MEMCTR 0x03F01 R/W Memory control register II-16
CKCTR 0x03F04 R/W Clock control register IV-6
AUCTR 0x03F07 W Extended calculation control register II-18
SBNKR 0x03F0A R/W Bank register for source address II-12
DBNKR 0x03F0B R/W Bank register for destination address II-12
NMICR 0x03FE1 R/W Non-maskable interrupt control register III-22
xxxICR
0x03FE2
to
0x03FFE
R/W Maskable interrupt control register
III-22
to
III-24
D1
15 0
Data register
D3
D0
D2
78
DW0
DW1
A0
15 0
Address register
A1
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