Panasonic MN101L Series

Chapter 20
Appendix
Instruction set XX - 5
20.2 Instruction set
Mnemonic
*1
*2
*3
*1
*2
*3
*4 *7
*4 *7
*2 *7
*2 *7
*3 *7
*3 *7
*7
*7
*7
*7
*7
*7
*7
*4 *7
*2 *7
*2 *7
*3 *7
*3 *7
*7
*7
*7
*7
*7
*7
*7
*7
*5
*6
1
1010
1010
1001
0001
0100
0110
0110
0110
0110
0110
0110
0100
0100
1100
0101
0111
0111
0111
0111
0111
0111
0101
0101
1101
0000
0001
0001
1101
1101
1110
1110
1110
1110
1110
1110
1110
1110
1100
1100
1100
1100
1111
1111
1111
1111
1111
1111
1111
1111
1101
1101
1101
1101
1001
1001
0000
0000
1100
2
DnDm
DmDm
01Dn
01Dm
1ADm
1ADm
1ADm
01Dm
01Dm
00Dm
00Dm
01Dm
00Dm
00Dm
1aDn
1aDn
1aDn
01Dn
01Dn
00Dn
00Dn
01Dn
00Dn
00Dn
0010
0100
0101
1001
00Dn
00Ad
10Aa
011d
010a
011d
010a
001d
000a
011d
010a
011d
010a
00ad
10aA
011D
010A
011D
010A
001D
000A
011D
010A
011D
010A
010D
011A
110d
111a
111d
3
<#8.
<d8.
<d16
<d4>
<d8.
<d16
<io8
<abs
<abs
<abs
<d8.
<d16
<d4>
<d8.
<d16
<io8
<abs
<abs
<abs
<io8
<abs
<abs
<abs
<d4>
<d4>
<d8.
<d8.
<d16
<d16
<abs
<abs
<abs
<abs
<d4>
<d4>
<d8.
<d8.
<d16
<d16
<abs
<abs
<abs
<abs
<#8.
<#8.
<#16
4
...>
...>
....
...>
....
...>
8..>
12..
16..
...>
....
...>
....
...>
8..>
12..
16..
...>
8..>
12..
16..
...>
...>
....
....
8..>
8..>
16..
16..
...>
...>
....
....
8..>
8..>
16..
16..
...>
...>
....
5
....
....
...>
....
....
....
...>
....
<#8.
<#8.
...>
....
....
....
....
....
....
....
....
....
....
6
...>
...>
...>
...>
...>
...>
...>
...>
<#8.
...>
...>
...>
...>
...>
...>
...>
...>
...>
...>
7
...>
<#8.
8
...>
9
10
11
Ext.
0010
0010
0010
0010
0010
0010
0010
0010
0010
0010
0011
0010
0010
0010
0010
0010
0010
0010
0010
0010
0010
0010
0010
0010
0010
REP
2
4
3
3
2
4
7
3
5
7
4
4
5
7
2
4
7
3
5
7
4
4
5
7
6
6
7
9
2
2
3
3
3
5
5
7
7
4
4
7
7
2
3
3
3
5
5
7
7
4
4
7
7
2
2
4
4
6
1
1
2
1
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
2+d
2+d
2+d
2+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1+d
1
1
1
Dn → Dm
imm8 → Dm
Dn → PSW
PSW → Dm
mem8(An) → Dm
mem8(d8+An) → Dm
mem8(d16+An) → Dm
mem8(d4+SP) → Dm
mem8(d8+SP) → Dm
mem8(d16+SP) → Dm
mem8(IOTOP+io8) → Dm
mem8(abs8) → Dm
mem8(abs12) → Dm
mem8(abs16) → Dm
Dn → mem8(Am)
Dn → mem8(d8+Am)
Dn → mem8(d16+Am)
Dn → mem8(d4+SP)
Dn → mem8(d8+SP)
Dn → mem8(d16+SP)
Dn → mem8(IOTOP+io8)
Dn → mem8(abs8)
Dn → mem8(abs12)
Dn → mem8(abs16)
imm8 → mem8(IOTOP+io8)
imm8 → mem8(abs8)
imm8 → mem8(abs12)
imm8 → mem8(abs16)
Dn → mem8(HA)
mem16(An) → DWm
mem16(An) → Am
mem16(d4+SP) → DWm
mem16(d4+SP) → Am
mem16(d8+SP) → DWm
mem16(d8+SP) → Am
mem16(d16+SP) → DWm
mem16(d16+SP) → Am
mem16(abs8) → DWm
mem16(abs8) → Am
mem16(abs16) → DWm
mem16(abs16) → Am
DWn → mem16(Am)
An → mem16(Am)
DWn → mem16(d4+SP)
An → mem16(d4+SP)
DWn → mem16(d8+SP)
An → mem16(d8+SP)
DWn → mem16(d16+SP)
An → mem16(d16+SP)
DWn → mem16(abs8)
An → mem16(abs8)
DWn → mem16(abs16)
An → mem16(abs16)
DWn → mem16(HA)
An → mem16(HA)
sign(imm8) → DWm
zero(imm8) → Am
imm16 → DWm
MOV Dn, Dm
MOV imm8, Dm
MOV Dn, PSW
MOV PSW, Dm
MOV (An), Dm
MOV (d8,An), Dm
MOV (d16,An), Dm
MOV (d4,SP), Dm
MOV (d8,SP), Dm
MOV (d16,SP), Dm
MOV (io8), Dm
MOV (abs8), Dm
MOV (abs12), Dm
MOV (abs16), Dm
MOV Dn, (Am)
MOV Dn, (d8,Am)
MOV Dn, (d16,Am)
MOV Dn, (d4,SP)
MOV Dn, (d8,SP)
MOV Dn, (d16,SP)
MOV Dn, (io8)
MOV Dn, (abs8)
MOV Dn, (abs12)
MOV Dn, (abs16)
MOV imm8, (io8)
MOV imm8, (abs8)
MOV imm8, (abs12)
MOV imm8, (abs16)
MOV Dn, (HA)
MOVW (An), DWm
MOVW (An), Am
MOVW (d4,SP), DWm
MOVW (d4,SP), Am
MOVW (d8,SP), DWm
MOVW (d8,SP), Am
MOVW (d16,SP), DWm
MOVW (d16,SP), Am
MOVW (abs8), DWm
MOVW (abs8), Am
MOVW (abs16), DWm
MOVW (abs16), Am
MOVW DWn, (Am)
MOVW An, (Am)
MOVW DWn, (d4,SP)
MOVW An, (d4,SP)
MOVW DWn, (d8,SP)
MOVW An, (d8,SP)
MOVW DWn, (d16,SP)
MOVW An, (d16,SP)
MOVW DWn, (abs8)
MOVW An, (abs8)
MOVW DWn, (abs16)
MOVW An, (abs16)
MOVW DWn, (HA)
MOVW An, (HA)
MOVW imm8, DWm
MOVW imm8, Am
MOVW imm16, DWm
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MOV
MOVW
Group
Notes
Operation
VF NF CF ZF
Code
Size
Execution
Cycle
Machine Code
Data Transfer Instructions
MN101L SERIES INSTRUCTION SET
Flag
*1 d8 sign-extention
*2 d4 zero-extention
*3 d8 zero-extention
*4 A = An, a = Am
*5 #8 sign-extention
*6 #8 zero-extention
*7 When the access address is odd number, the execution cycle is added "( 1 + d )" .