Panasonic MN101L Series

Chapter 20
Appendix
XX - 4 Symbol Definitions
 List of symbols used in flag changes
"flag" is a general term of lower 4-bit (VF, NF, CF, ZF) of PSW.

Execution cycle
Execution cycle may change depending on the status of the pipeline and the memory space to access.
Execution cycle described in this chapter is based on the following conditions;
The execution cycle considers the instruction fetch wait cycle and the data load /store wait cycle. the
instruction fetch wait cycle and the data load /store wait cycle depend on the resources to access.
Refer to [LSI manual] for details.
And, it may increase by the pipeline stall (instruction supply shortfall, register conflict, etc.).
Refer to [MN101L Series Instruction Manual] for details.
EX.1 BSET (abs8)bp Cycle: 2+2d
If the data access cycle is 1 (d = 0), then the execution cycle becomes 2 + 2 * 0 = 2 cycles.
If the data access cycle is 3 (d = 2), then the execution cycle becomes 2 + 2 * 2 = 6 cycles.
EX.2 JSR label Cycle: max(2+i, 4+2d)
If the instruction fetch cycle is 2 (i = 1) and the data access cycle is 1 (d = 0),
then the execution cycle becomes (2 + 1, 4 + 2 * 0) = 4 cycles.
mem16(xxx) : 16-bit data in the memory specified by xxx
sign(xxx) : Sign-extended data of xxx
zero(xxx) : Zero-extended data of xxx
d4(label) : 4-bit displacement between PC and label ( -16 to +15 nibbles )
d7(label) : 7-bit displacement between PC and label ( -128 to +127 nibbles )
d11(label) : 11-bit displacement between PC and label ( -1024 to +1023 nibbles )
d12(label) : 12-bit displacement between PC and label ( -2048 to +2047 nibbles )
d16(label) : 16-bit displacement between PC and label ( -65536 to +65535 nibbles )
RPC : Repeat counter
H : Half-byte bit
i : Instruction fetch wait cycle
d : Data load / store wait cycle
max(a, b) : Execution cycle ( the maximum value in listed number ( a, b ) is effective. )
z : flag changes
— : no flag changes
0
: flag is always
"0"
1
: flag is always
"1"