Chapter 14
DMA Controller
DMA Data Transfer XIV - 13
14.3.2 Burst Transfer Mode
When the DMA start trigger occurs, data, the size of which is decided with DMCTR0H.DMUT, is transferred in a
single burst until the data transfer counter consisting of DMACNTH and DMACNTL are decremented to zero.
When all the data transfer finishes, DMA interrupt occurs.
If the DMA start trigger happens during the time after DMA reads the last burst data from Source Address and
before the DMCTR1L.DMTEN is set to "1" by software (for example, the period (B) in the Figure 14.3.2), DMA-
AddReq interrupt occurs.
If the DMA start trigger happens during the time after the DMA start trigger occurs and before DMA reads the
last data) from Source Address (for example, the period (A) in the Figure 14.3.2), DMA-Error interrupt occurs.
Figure:14.3.2 Example of Burst Transfer
Read Write
DMA
start trigger
DMA
interrupt
DMCNTH
DMCNTL
4
DMA
Memory Access
Read Write Read Write
Period (A)
32
DMTEN of
DMCTR1L
When DMA interrupt occurs,
the DMTEN is cleard to "0" by hardware.
0 N
Set the DMTEN to "1"
by software for next DMA.
Period (B)
Read Write
1
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