Panasonic MN101L Series

Chapter 3
Interrupts
Overview III - 3
3.1.1 Block Diagram
Figure:3.1.1 Interrupt Block Diagram
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Interrupt
IRQNMI
level
deter-
mination
IM1
IRQLVL
2-0
IM0
NMICR
Vector 1
Vector 2
Vector N
Vector 30
WDTOVF
IRQ0ICR
IE IR
LV1-0
External interrupt 0
0
1 DEC
2
PERI1ICR
0
1 DEC
2
PSW
CPU
Undefined
Instruction
MIE
LV1-0
Vector 29
Group-0 interrupt
Group-1 interrupt
PERI0ICR
0
1 DEC
2
LV1-0