Panasonic MN101L Series

Chapter 2
CPU
II - 14 Bus Interface
2.2 Bus Interface
2.2.1 Bus Controller
The CPU provides separate buses to the internal memory and internal peripheral circuits to reduce bus line loads
and thus realize faster operation.
There are three buses: ROM bus, RAM bus, and peripheral extension bus (C-BUS). They connect to the internal
ROM, internal RAM, internal peripheral circuits respectively. The bus control block controls the parallel opera-
tion of instruction read and data access. Figure:2.2.1 shows functional block diagram of the bus controller.
Figure:2.2.1 Functional Block Diagram of the Bus Controller
Operand address
MUX
Internal ROM Internal RAM
Instruction
queue
Interrupt bus
Instruction
input bus
Data input bus
Data output bus
Interrupt
control
Program address
Address decoder
Memory control register
Memory mode setting
MUX MUX
Internal peripheral
functions
ROM bus RAM bus
AD AD
Peripheral extension
bus(C-BUS)
Bus controller
AD