Chapter 2
CPU
II - 2 Overview
2.1 Overview
The AM13L core (CPU), upward compatible with MN101C/E core, has the enhanced calculation units, shortens
the interrupt latency and has the 16-bit bus architecture to access instruction/data memory and peripheral circuits.
The CPU executes most of instructions in one clock cycle, and achieves high performance comparable to a 16-bit
microcomputers.
Table:2.1.1 Basic Specifications of CPU
Structure
Load / Store architecture
Registers
Data: 8-bit × 4
Address: 16-bit × 2
Others
SP: 16 bits
PC: 21 bits
PSW: 8 bits
Instructions
Number of instructions 39
Addressing modes 9
Instruction length
Basic portion: 1-byte ( Min.)
Extended portion: 0.5-byte × n ( 0 ≤ n ≤ 10 )
Basic performance
Internal operating frequency ( Max. ) 10 MHz
Instruction execution Min. 1 cycle
Register to register operation Min. 1 cycle
Load / Store Min. 1 cycle
Condition branch non-branching 1 cycle / branching 3 cycles
Pipeline 3-stage ( instruction fetch, decode, execution ), 4-stage (memory access)
Address space
128 KB ( Data area: 64 KB × 2 banks )
One shared memory for Instruction and data
Interrupt Vector interrupt, 3 interrupt levels
Low-power
consumption mode
STOP mode, HALT mode
To Next Page
Loading...
