Panasonic MN101L Series

Chapter 10
General-Purpose Time Base/Free-Running Timer
X - 14 Time Base Timer
10.4.2 Setup Example
 Timer Operation Setup (Time Base Timer)
The time base timer generates interrupts regularly by selecting a interrupt generation cycle. The interrupt genera-
tion cycle is f
HCLK
× 1/2
13
(1.024 ms: f
HCLK
= 8 MHz).
The setup procedure and the description of each step are shown below.
• When the selected interrupt cycle elapsed, the time base interrupt request bit (PERI0DT2) of the interrupt con-
trol register for
peripheral function Group 0 (PERI0DT) is set to "1".
Setup Procedure Description
(1) Select the clock source
TM6MD (0x03F7A)
bp0: TM6CK0 = 0
(1) Select HCLK as a clock source by the TM6CK0 bit of the
timer 6 mode register (TM6MD).
(2) Disable the interrupt
PERI0EN (0x03FDC)
bp2: PERI0EN2 = 0
(2) Set the PERI0EN2 bit of the PERI0EN register to "0" to
disable the interrupt.
(3) Select the interrupt generation cycle
TM6MD (0x03F7A)
bp6-4 :TM6IR2-0 = 101
(3) Set the TM6IR2-0 bits of the TM6MD register to select
the specified clock × 1/2
13
as an interrupt generation
cycle.
(4) Initialize the time base timer
TBCLR (0x03F7B) = 0x00
(4) Write an arbitrary value to the time base timer clear
control register (TBCLR) to initialize the time base
timer.
(5) Set the interrupt level
PERI0ICR(0x03FEB)
bp7-6: G11LV1-0 = 01
(5) Set the PERI0LV1-0 bits of the peripheral function group
0 interrupt level control register (PERI0ICR) to select
the interrupt level. Clear the corresponding interrupt
request bit of PERI0DT register, if it may have already
been set.
[3.1.5 Set up procedure for Interrupt control register for
peripheral function group]
(6) Enable the interrupt
PERI0EN (0x03FDC)
bp2: PERI0EN2 = 1
(6) Set the PERI0EN2 bit of the PERI0EN register to "1" to
enable the interrupt.
(7) Start the time base timer operation
TM6BEN (0x03F7C)
bp1: TBEN = 1
(7) Set the TBEN bit of the TM6BEN register to "1" to start
the time base timer.