Panasonic MN101L Series

Chapter 13
Serial Interface
Overview XIII - 5
13.1.2 Block Diagram
Figure:13.1.1 SCIFn (n = 0, 1) Block Diagram
Reception shift register
UART:start bit added UART:stop bit added UART:parity added UART:break transmission Clock Synchronous:last data set selection
Transmission control circuit
Prescaler
Transmit shift register
Transmission buffer
SCnMD0.SCnCE1 SCnMD1.SCnSBTS
SCnMD0.SCnDIR
SCnMD1.SCnSBIS
Read/Write
SCnRDB
SCnTRB
RXBUFn TXBUFn
SWAP MSB<->LSB
HCLK/SCLK/SYSCLK
Clock I/O pin
S E
L
SBOn
S E L
1/2
BRTM
Counter
Compare register
BRTM_Sn_OC
BRTM_S_EN.BRTM_Sn_EN
BRTM_S_MD.BRTM_Sn_MD
BRTM_S_CKSEL BRTM_S01_CK
SCnMD1.SCnIOM
Reception buffer
Comparator
Prescaler
BRTM_SCn_SCLK
(BRTM output clock)
SCnMD1.SCnMST
SBOnA SBOnB
S E
L
SC01SEL.SCnSEL1
SCnMD1.SCnCKM SCnMD1.SCnDIV
SCnMD2.SCnFM1-0 SCnMD2.SCnPM1-0 SCnMD2.SCnBRKE SCnMD3.SCnFDC1-0
Baud rate timer(BRTM)
UART:Break reception(SCnMD2.SCnBRKF) UART:Frame error detection(SCnSTR.SCnFEF) UART:Parity error detection(SCnSTR.SCnPEK) Clock Synchronous,UART:Overrun error detection(SCnSTR.SCnORE)
Reception control circuit
I/O control
Polar control
Data input pin
SCnMD1.SCnSBOS
Data output pin
SBOn
SBIn
SBInA SBInB
S E
L
SC01SEL.SCnSEL0
SBTn
SBTnA SBTnB
S E
L
SC01SEL.SCnSEL2
S E
L
I/O control
SBOnA SBOnB
S E L
SC01SEL.SCnSEL1
Chip select I/O pin
SBTn
SBTnA SBTnB
S E L
SC01SEL.SCnSEL3
Chip select
generation circuit
SCnMD1.SCnMST
I/O control
Polar control