Panasonic MN101L Series

Chapter 9
16-bit Timer
IX - 30 16-bit Timer Pulse Output
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In the initial state after releasing reset, the timer pulse output is reset and fixed to "Low".
Therefore, release the reset of the timer pulse output by setting the TMnMD1.TMnCL to "0".
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Regardless of whether TMnBC is stopped or in active, the timer output becomes "Low", when
the TMnMD1.TMnCL is set to "1".
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Release the reset of the timer pulse output when the timer count is stopped.
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9.5.2 Setup Example
 Timer Pulse Output Setup Example
Here is an example that, using Timer 7, a 50 kHz pulse is output from TM7IOA pin. In order to output a 50 kHz
pulse, select HCLK for clock source, and set 1/2 cycle (100 kHz) in the Timer 7 compare register.
HCLK (at f
HCLK
= 8 MHz) is selected as a clock source.
The setup procedure and its description are shown below.
Step Setting Register Description
1 Disable the timer counter TM7MD.TM7EN = 0 Disable the timer count operation.
2 Select the timer output pin TMIOEN1.TM7OEN = 1 Select the timer output pin.
[Chapter 7 I/O Port]
3 P0DIR.P0DIR4 = 1
4 Set the timer mode register TM7MD2.TM7PWM = 0 Select the timer output.
5 TM7MD2.TM7BCR = 1 Select the TM7BC clear source.
6 TM7MD1.TM7CL = 0 Enable the timer output.
7
TM7MD1.TM7CK1-0 = 00
TM7MD1.TM7PS1-0 = 00
Select HCLK as the count clock source.
8
Set the output cycle TM7PR1 = 0x004F Set the timer output cycle.
Setup value: 80 - 1 = 79 (0x004F)
9 Enable the timer counter TM7MD1.TM7EN = 1 Enable the timer count operation.