Chapter 2
CPU
Reset II - 29
2.5.2 Reset sequence
1. When NRST pin comes to high level from low level, the internal binary counter starts counting.
The time range after the counter started counting before the overflow of it occurs is called the "oscillation sta-
bilization wait time". During reset, internal registers and special function registers are initialized.
2. After the oscillation stabilization wait time, the internal reset is released and the CPU starts executing the pro-
gram, the address of which is shown in the interrupt vector table at 0x04000.
..
The internal RAM is not initialized at reset.
It needs to be initialized before used.
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