Panasonic MN101L Series

Chapter 15
Buzzer
XV - 2 Overview
15.1 Overview
Buzzer circuit outputs the square wave generated by dividing HCLK by 1/2
9
to 1/2
14
or SCLK by 1/2
3
to 1/2
4
.
Figure:15.1.1 Buzzer Block Diagram
BUZCTR.BUZS2-0
BUZCTR.BUZS2-0
BUZCTR.BUZOE
Output
Control
Clock Divider
BUZCTR.BUZOE
Reset
R
MUX
HCLK
SCLK
Count Clear
Controller
Buzzer Output(BUZA/BUZB)
Inverted Buzzer Output(NBUZA/NBUZB)
f
HCLK /2
14
f HCLK /2
13
f HCLK /2
12
f HCLK /2
11
f HCLK /2
10
f HCLK /2
9
f SCLK /2
4
f SCLK /2
3